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Module 2: The 8051 Architecture

20253.5m

Explain the address bus, data bus, and control bus in the 8051 architecture.

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Address, Data, Control Bus in 8051

  • Address Bus (16-bit, unidirectional): A15-A8 via P2 (high) stable, A7-A0 via P0 multiplexed→latch. Selects 64K program/data.
  • Data Bus (8-bit, bidirectional): D7-D0 via P0 after ALE, carries data CPU↔memory/peripherals. Shared with address time-multiplexed.
  • Control Bus: ALE (latch), \overline{PSEN} (program read), \overline{RD}/\overline{WR} (P3.7/6 data read/write), \overline{EA}, RST, INTx. Generated by timing & control unit from clock. Manage direction and timing.

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