MICROPROCESSORS

Answer: (i) Via I/O ports

Explanation: 8051 communicates with external peripherals/memory via its 32 I/O lines (P0-P3). Port 0 & Port 2 provide multiplexed address/data buses, Port 3 provides control signals (RD, WR), while data transfer occurs through port pins. Register arrays are internal.

Answer: (i) Through demultiplexing by external latch & ALE signal

Explanation: Port 0 multiplexes A0-A7/D0-D7. At start of external memory cycle, ALE high latches A0-A7 into 74LS373. When ALE falls, Port 0 becomes data bus. Thus address and data are demultiplexed using external latch driven by ALE. Not DLE, not multiplexing.

Interface 16 KB ROM + 8 KB RAM with 8051

8051 has separate program (\overline{PSEN}) and data (\overline{RD}/\overline{WR}) spaces, each 64KB. Typically ROM as program memory and RAM as data memory.

Option 1: Both as program/data expansion using external memory (most exam expects unified external):

• 16 KB ROM (e.g., 27128): Needs 14 address lines A0-A13. Connected to P0 (AD0-AD7 latched) + P2.0-P2.5 (A8-A13). \overline{PSEN} or \overline{RD} as OE. Address range example if starting at 0000H:
  0000H – 3FFFH (16384 bytes) for 16KB.
  Next free from 4000H.
• 8 KB RAM (e.g., 6264): Needs 13 lines A0-A12. If contiguous after ROM:
  4000H – 5FFFH (8192 bytes) for 8KB.
  Using \overline{RD} and \overline{WR} for OE/WE. Chip select via decoder (74LS138) or simple linear P2.6/P2.7.

Full decoding example via 74LS138 (A15-A13):

• ROM CS = Y0 → 0000H-1FFFH for 8K? But for 16K, use A14=0 block. Simpler: A15=0 for lower 32K. Many textbooks show:
  ROM 16K: 0000H–3FFFH ( \overline{PSEN} ), RAM 8K: 8000H–9FFFH (using P2.7=1) to avoid overlap with different spaces. Because program and data spaces are separate, same address can be reused; the range is logical. If both as data memory (MOVX), same ranges but using \overline{RD}/\overline{WR}.

Hardware: Port 0 via 74LS373 latched by ALE provides A0-A7, Port 2 provides A8-A15, \overline{EA}=1 for internal + external, or 0 for only external. Connect ROM OE to \overline{PSEN} (program) or RAM OE to \overline{RD}.

Address map summary (one common textbook arrangement):

• 16KB ROM: 0000H to 3FFFH
• 8KB RAM: 4000H to 5FFFH (or 0000H-1FFFH in data space if separate buses - then no conflict)
  Calculation: 16KB=2^14 → last = start+3FFFH; 8KB=2^13 → last = start+1FFFH.
  If you place RAM at 0000H data space, its range is 0000H-1FFFH distinct from program ROM.

Diagram: P0→373→A0-A7→ROM/RAM, P2→A8-A15, ALE→373 LE, \overline{PSEN}→ROM OE, \overline{RD}/\overline{WR}→RAM OE/WE, CS decoded from high address lines.

Any contiguous non-overlapping 14-bit/13-bit block is acceptable if decoding explained.

Timer Circuit & Operations in 8051

8051 has two 16-bit timers/counters T0/T1 (8052 adds T2). Each has THx/TLx, controlled by TMOD (GATE, C/T, M1,M0) and TCON (TFx, TRx).

Modes: Mode0 13-bit, Mode1 16-bit, Mode2 8-bit auto-reload, Mode3 split TL0/TH0 as two 8-bit (T1 stops).

Timer vs Counter: Timer counts machine cycles (Fosc/12, internal), Counter counts external pulses on T0 (P3.4)/T1 (P3.5) falling edge.

Operation: Set TMOD e.g., MOV TMOD,#01H (T0 mode1 timer), load THx/TLx =65536-counts, SETB TRx starts, TFx sets on overflow (interrupt if ET0/1+EA). GATE=1 allows INTx pin gating.

Baud use: Timer1 mode2 auto-reload for serial baud. Programming example for delay as in Q12.

Control via TCON bits.

Memory Interfacing Techniques in 8051

• Linear/Low-cost: Direct high line to CS (e.g., P2.7 to ROM CS) → simple but wastes space, partial decoding.
• Full Decoding: 74LS138 decoder from A15-A13 to select multiple devices, non-overlapping ranges (e.g., Y0 0000-1FFFH for 8K ROM, Y1 2000-3FFFH for RAM).
• Bus Multiplexing: P0 AD0-7 via 74LS373 latched by ALE, P2 provides high address; \overline{PSEN}→ROM OE, \overline{RD}/\overline{WR}→RAM OE/WE.
• Program vs Data: ROM to \overline{PSEN} space, RAM to MOVX space; can share same physical chip with separate controls.
• **Example 16K ROM (27128) +8K RAM (6264) decoding as Q11: ROM 0000-3FFFH, RAM 4000-5FFFH.

ADC Interfacing with 8051 (e.g., ADC0804/0808)

Connections: ADC0804: CS\→P3.3, RD\→P3.7 (\overline{RD}), WR\→P3.6 (\overline{WR}), INTR\→P3.2 (INT0) or polled on P2.0, Vref/2, CLK RC, Vin → analog sensor, D0-D7 → P1. Start conversion: WR low pulse, wait INTR low (conversion done), read: RD low, data on P1. For ADC0808 with 8 channels, add A,B,C→P2.0-2 & ALE via latch, EOC→poll.

Program (polling):

START: CLR P3.6 ; WR low
       SETB P3.6 ; WR high start
WAIT:  JB P3.2,WAIT ; INTR high while busy
READ:  CLR P3.7 ; RD low → enable output
       MOV A,P1 ; read digital
       SETB P3.7
       MOV P2,A ; display or store

Also via interrupt ISR on INT0. Succession approx 100µs. Send to LCD/serial as needed.

LCD Interfacing with 8051 (16×2 HD44780)

Hardware: Data D0-D7 → P1 (or 4-bit D4-D7→P1.4-7), RS→P2.0, RW→P2.1, EN→P2.2, Vee via 10k pot contrast, VCC/GND. Backlight via transistor.

Initialization (8-bit mode):

MOV A,#38H ; 8-bit, 2 line, 5×7
ACALL CMD
MOV A,#0EH ; display ON, cursor ON
ACALL CMD
MOV A,#01H ; clear
ACALL CMD
MOV A,#06H ; entry auto-increment
ACALL CMD

CMD/DTA: RS=0/RW=0 pulse EN for command, RS=1 for data. Delays 1-2ms.

Display: Send ASCII data writes via MOV P1,A + EN pulse. Busy flag check optional (RW=1). Common library lcd_init, lcd_data. Wiring description suffices for diagram.

Short Notes: Counters (8051)

• Timers configured as counters when C/T=1 in TMOD count pulses on T0 (P3.4)/T1(P3.5) falling edge.
• 16-bit count up; overflow TFx→interrupt.
• Modes as timers: 13/16/8-bit auto-reload/split.
• Used to count external events: pulse counting, frequency measure.
• Example: TMOD=06H (T1 counter mode2) counts external.

Short Notes: Timers/Counters – see Q124

2×16-bit T0/T1, TMOD/TLx/THx/TCON, modes 0-3, timer = Fosc/12, counter = external T0/T1 pulses, overflow TF→interrupt, used for delay, baud, event count.

Short Notes: Memory Interfacing – see Q152

Demultiplex P0 via 74LS373 + ALE, P2 high address, decoding via 74LS138, \overline{PSEN}→ROM, \overline{RD}/\overline{WR}→RAM, full vs linear decoding, example 16K ROM 0000-3FFFH +8K RAM etc.

Wait States in Memory Interfacing

• Definition: Extra clock/T-states inserted when slow memory/peripheral cannot respond within CPU’s default memory cycle.
• Why: 8051’s default external fetch expects memory to output data within ∼3 T-states after RD/PSEN; slower EPROM/IO may need more.
• Implementation: In 8051 classic, no programmable wait-state, but designer can stretch cycle via READY pin on derivatives, or use slower ALE timing, or insert NOP/Dummy cycles, or use external wait logic pulling READY/ALE. Modern 8051 derivatives add SFR bits to insert 1-3 wait states.
• Effect: Reduces bus speed but ensures reliable read; backup is using faster memory.