Two Techniques for Enhancing Performance with Multiple Execution Pipelines

Multiple execution pipelines (superscalar / superpipelined architecture) allow Instruction Level Parallelism (ILP) by executing more than one instruction per clock. Two key techniques:

1. Superscalar Execution (Multiple Issue Pipeline)

• Concept: Processor contains $m$ parallel pipelines (e.g., Integer pipe, FP pipe, Load/Store pipe). In each cycle, issue logic fetches and issues $n$ instructions simultaneously ($n$-way superscalar) if no dependencies.
• Hardware required:
  • Multiple functional units: ALU1, ALU2, FPU, Branch unit, Load/Store unit
  • Instruction Fetch & Decode capable of $n$ instructions/cycle
  • Dependency checking / Scoreboarding / Tomasulo algorithm to detect data hazards (RAW, WAR, WAW)
  • Register renaming to remove false dependencies
• Example: 2-way superscalar can issue ADD R1,R2,R3 and MUL R4,R5,R6 together if independent.
• Advantage: Increases throughput ideal CPI $\to 1/n$ (e.g., CPI 0.5 for 2-way). Exploits ILP without compiler support (dynamic).
• Limitation: Complex issue logic, requires out-of-order execution and large window; limited by true dependencies and branches.

2. Superpipelining and Out-of-Order / Speculative Execution (Complementary techniques)

Often paired with superscalar; other major technique is VLIW-like / Superpipelined + Branch Prediction & Speculative Execution (can also be answered as Superpipelining or VLIW).

a) Superpipelining:

• Divides pipeline into many finer stages (e.g., 8-10 stages vs classic 5-stage: IF1, IF2, ID1, ID2, EX1, EX2, WB). Clock period = 1/m of base, so multiple instructions are in different sub-stages of same functional pipe - higher clock rate.
• Combination Superscalar + Superpipelining = Super-speculative processor (e.g., Pentium 4).

b) Out-of-Order Execution + Register Renaming + Speculative/Branch Prediction (essential to keep multiple pipelines busy):

• Multiple pipelines stall on hazards/branches. Solution:
  • Register Renaming: maps architectural registers to larger physical register file to eliminate WAR/WAW, allowing parallel execution.
  • Out-of-Order Execution: Instructions wait in Reservation Stations; execute as soon as operands ready, not program order. ReOrder Buffer (ROB) commits in order.
  • Branch Prediction + Speculative Execution: Predict branch direction (2-bit predictor, BTB) and speculatively execute down predicted path to keep pipelines filled. On mispredict, flush.
  • Dynamic Scheduling: Tomasulo / Scoreboard.

Alternative valid answer - VLIW (Very Long Instruction Word):
Compiler packs $k$ independent operations into one very long instruction word (e.g., 128-256 bit). Hardware is simple (no dependency check), compiler does static scheduling. Example: IA-64/Itanium. Merits: simple hardware; Demerits: poor code density, compiler dependent, binary incompatibility.

Performance gain summary: With $N$ pipelines ideal speedup $\to N$ if hazards avoided. Combination of ** Superscalar (space parallelism) + Superpipelining (time parallelism) + OOO/Speculation/Renaming** yields practical speedup 1.5x-3x per core.

Feature	Superscalar	Superpipeline/VLIW
Parallelism	Space - multiple pipes	Time - finer clocks / compiler-packed
Dependency check	Hardware dynamic	VLIW: Compiler static
Complexity	High hardware	VLIW: simple HW, complex compiler