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Module 3: Pipelining

20232m

The performance of a pipelined processor suffers if
(i) The pipeline stages have different delays
(ii) Consecutive instruction are dependent on each other
(iii) The pipeline stages share hardware resources
(iv) All of these

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Answer: (iv) All of these

Explanation:
Pipeline performance (Ideal CPI=1) degrades due to:

  1. Different stage delays: Clock period is set by slowest stage; faster stages idle => loss of efficiency. Unequal delays create bottlenecks/bubbles.
  2. Consecutive instruction dependency (Data hazard): RAW/WAR/WAW dependencies force stalls or forwarding.
  3. Shared hardware resources (Structural hazard): e.g., single memory for instruction & data, single ALU; simultaneous use by two stages causes conflict/stall.

All three cause pipeline stalls/NOPs, reducing speedup < number of stages. Hence (iv).

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