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Module 3: Pipelining

20192m

In case of pipelining processor, loop buffer is

  • (i) very high speed memory maintained by the instruction fetch stage
  • (ii) very high speed memory maintained by the instruction decode stage
  • (iii) very high speed memory maintained by the instruction execute stage
  • (iv) None of the above
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PreviousThe sequence of events that happen during a typical fetch operation is - (i) PC → MAR → Memory → MDR → IR - (ii) PC → Memory → MDR → IR - (iii) PC → Memory → IR - (iv) PC → MAR → Memory → IRNextThe average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is * (i) 55 ns * (ii) 45 ns * (iii) 90 ns * (iv) 19 ns