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COMPUTER ORGANIZATION & ARCHITECTUREThe performance of a pipelined processor suffers if (i) The pipeline stages have different delays (ii) Consecutive instruction are dependent on each other (iii) The pipeline stages share hardware resources (iv) All of these20232mCOMPUTER ORGANIZATION & ARCHITECTUREWhich of the following holds data and processing instructions temporarily until the CPU needs it? * (i) ROM * (ii) Control unit * (iii) Main memory * (iv) Coprocessor chip20192mCOMPUTER ORGANIZATION & ARCHITECTUREPipeline speedup ideally increases with: (i) Number of control units (ii) Size of RAM (iii) Number of pipeline stages (iv) Size of cache20252mCOMPUTER ORGANIZATION & ARCHITECTUREWhat is meant by pipelining? Why do we require instruction pipelining? Explain its working procedure. Discuss the pipeline performance measures.201614m
Previous(b) How is virtual memory managed using paging and TLB? Explain with suitable example.NextThe sequence of events that happen during a typical fetch operation is - (i) PC → MAR → Memory → MDR → IR - (ii) PC → Memory → MDR → IR - (iii) PC → Memory → IR - (iv) PC → MAR → Memory → IR
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