Answer: (iii) Number of pipeline stages

Explanation:
Ideal pipeline speedup (ignoring hazards and overhead) is:

$$Speedup = \frac{T_{non-pipelined}}{T_{pipelined}} \approx k$$

where $k$ = number of stages, or more precisely for $n$ tasks:

$$S = \frac{n \times k \times t_p}{k \times t_p + (n-1) \times t_p} \approx k \text{ for large } n$$

where $t_p$ = stage delay. Throughput increases because multiple instructions overlap in different stages simultaneously.

• (iii) is correct: More stages → finer subdivision → more instructions overlapped → higher ideal speedup (linear with $k$). Example: 5-stage RISC pipeline ideally gives ~5x speedup.

• Why others are wrong:

  • (i) Number of control units - pipelining uses one control unit with stages, not multiple CUs.
  • (ii) Size of RAM / (iv) Size of cache - affects memory performance, not pipeline speedup directly.

Note: Practical speedup < $k$ due to pipeline hazards (data, control, structural), branch penalties, and latch overhead, so deeper pipeline gives diminishing returns.