2025 question paper
COMPUTER ORGANIZATION & ARCHITECTURE
26 questions
Q1a. The unit responsible for fetching, decoding, and executing instructions is: (i) ALU (ii) Memory Unit (iii) Control Unit (iv) I/O Unit20252m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →The unit responsible for fetching, decoding, and executing instructions is:
(i) ALU
(ii) Memory Unit
(iii) Control Unit
(iv) I/O UnitQ1b. Which addressing mode uses the contents of a register to determine the effective address? (i) Signed integers (ii) Indirect addressing (iii) Direct addressing (iv) Register addressing20252m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Which addressing mode uses the contents of a register to determine the effective address?
(i) Signed integers
(ii) Indirect addressing
(iii) Direct addressing
(iv) Register addressingQ1c. Two's complement representation is primarily used for: (i) Signed integers (ii) Instruction opcodes (iii) ASCII characters (iv) Floating point numbers20252m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Two's complement representation is primarily used for:
(i) Signed integers
(ii) Instruction opcodes
(iii) ASCII characters
(iv) Floating point numbersQ1d. Booth's algorithm is used for: (i) Floating point operations (ii) Character coding (iii) Division (iv) Multiplication20252m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Booth's algorithm is used for:
(i) Floating point operations
(ii) Character coding
(iii) Division
(iv) MultiplicationQ1e. In floating point representation, the part representing significant digits is called: (i) Mantissa (ii) Exponent (iii) Sign bit (iv) Base20252m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →In floating point representation, the part representing significant digits is called:
(i) Mantissa
(ii) Exponent
(iii) Sign bit
(iv) BaseQ1f. x86 architecture belongs to which processor family? (i) RISC (ii) CISC (iii) EPIC (iv) ARM20252m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →x86 architecture belongs to which processor family?
(i) RISC
(ii) CISC
(iii) EPIC
(iv) ARMQ1g. Memory chips used in main memory are typically: (i) Optical memory (ii) Flash (iii) Magnetic tapes (iv) DRAM20252m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Memory chips used in main memory are typically:
(i) Optical memory
(ii) Flash
(iii) Magnetic tapes
(iv) DRAMQ1h. USB is an example of: (i) Networking device (ii) Storage device only (iii) Standard I/O interface (iv) Wireless protocol20252m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →USB is an example of:
(i) Networking device
(ii) Storage device only
(iii) Standard I/O interface
(iv) Wireless protocolQ1i. Pipeline speedup ideally increases with: (i) Number of control units (ii) Size of RAM (iii) Number of pipeline stages (iv) Size of cache20252m
Module 3: Pipelining
View this question on its own page →Pipeline speedup ideally increases with:
(i) Number of control units
(ii) Size of RAM
(iii) Number of pipeline stages
(iv) Size of cacheQ1j. In cache memory, FIFO and LRU are examples of: (i) Mapping techniques (ii) Addressing techniques (iii) Replacement algorithms (iv) Write policies20252m
Module 4: Memory Organization
View this question on its own page →In cache memory, FIFO and LRU are examples of:
(i) Mapping techniques
(ii) Addressing techniques
(iii) Replacement algorithms
(iv) Write policiesQ2a. Explain the functional blocks of a computer with a neat diagram (CPU, Memory, I/O).20257m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Explain the functional blocks of a computer with a neat diagram (CPU, Memory, I/O).
Q2b. Explain addressing modes with examples. Compare at least five different addressing techniques.20257m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain addressing modes with examples. Compare at least five different addressing techniques.
Q3a. Explain all types of number representations: signed integers, fixed point, floating point, and character codes.20257m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Explain all types of number representations: signed integers, fixed point, floating point, and character codes.
Q3b. Describe floating point arithmetic and explain overflow, underflow, normalization, and rounding.20257m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Describe floating point arithmetic and explain overflow, underflow, normalization, and rounding.
Q4a. Describe shift-and-add multiplication and Booth's multiplication algorithm with examples.20257m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Describe shift-and-add multiplication and Booth's multiplication algorithm with examples.
Q4b. Explain the architecture of x86 processors. Discuss its registers, addressing modes, and instruction format.20257m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain the architecture of x86 processors. Discuss its registers, addressing modes, and instruction format.
Q5a. Describe the design of a simple hypothetical CPU including instruction set, datapath, and control design.20257m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Describe the design of a simple hypothetical CPU including instruction set, datapath, and control design.
Q5b. Explain semiconductor memory organization with diagrams.20257m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain semiconductor memory organization with diagrams.
Q6a. Explain I/O transfer techniques: program-controlled I/O, interrupt-driven I/O, and DMA.20257m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain I/O transfer techniques: program-controlled I/O, interrupt-driven I/O, and DMA.
Q6b. Describe different types of interrupts: hardware, software, vectored, non-vectored, and exceptions.20257m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Describe different types of interrupts: hardware, software, vectored, non-vectored, and exceptions.
Q7a. Explain the basic concepts of pipelining, including speedup and throughput. Discuss pipeline hazards.20257m
Module 3: Pipelining
View this question on its own page →Explain the basic concepts of pipelining, including speedup and throughput. Discuss pipeline hazards.
Q7b. Describe parallel processors and the problem of cache coherency in shared memory systems.20257m
Module 3: Pipelining
View this question on its own page →Describe parallel processors and the problem of cache coherency in shared memory systems.
Q8a. Explain cache memory organization. Discuss mapping techniques (direct, associative, set-associative), replacement algorithms, and write policies.20257m
Module 4: Memory Organization
View this question on its own page →Explain cache memory organization. Discuss mapping techniques (direct, associative, set-associative), replacement algorithms, and write policies.
Q8b. Explain signed number representation using sign-magnitude, 1's complement, and 2's complement. Include advantages and disadvantages of each.20257m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Explain signed number representation using sign-magnitude, 1's complement, and 2's complement. Include advantages and disadvantages of each.
Q9a. Explain the organization of semiconductor memories such as SRAM and DRAM. Discuss refresh cycles, access times, and their applications.20257m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain the organization of semiconductor memories such as SRAM and DRAM. Discuss refresh cycles, access times, and their applications.
Q9b. Discuss memory hierarchy design principles. Explain how access time, cost, and size influence memory organization.20257m
Module 4: Memory Organization
View this question on its own page →Discuss memory hierarchy design principles. Explain how access time, cost, and size influence memory organization.