Solution - I/O Transfer Techniques

Three modes by which CPU communicates with I/O devices:

1. Program-Controlled I/O (Programmed I/O / Polling):

• CPU directly controls transfer under program. CPU executes I/O instruction, checks (polls) device status register (Busy/Ready flag) in a loop and transfers data when ready.
• Flow: CPU initiates I/O -> polls status -> if Ready, transfer 1 byte/word -> update count -> repeat.
• Types: Synchronous and Asynchronous; Memory-mapped vs Isolated I/O.
• Advantages: Simple hardware, no extra controller needed.
• Disadvantages: CPU busy waiting (wastage), very slow for fast devices, throughput low. CPU cannot do other work.
• Use: For slow devices like keyboard, or when data rate low.

2. Interrupt-Driven I/O:

• Removes polling waste. Device interrupts CPU only when ready to transfer.
• Flow: CPU initiates I/O and continues other work. Device when ready sends Interrupt Request (INTR) -> CPU completes current instruction -> saves PC/PSW -> executes Interrupt Service Routine (ISR) to transfer data -> restores context (IRET).
• Hardware: Requires Interrupt Controller (PIC e.g., 8259), interrupt vector table, enable/disable logic.
• Advantages: CPU utilization improves drastically vs polling; suitable for handling multiple devices with priority.
• Disadvantages: Still byte-by-byte transfer through CPU registers (CPU involved per word); context switch overhead per interrupt; not efficient for high-speed block transfers (disks).
• Variants: Vectored vs Non-vectored, priority interrupts (daisy chain).

3. Direct Memory Access (DMA):

• For high-speed block transfers (disk, network), a dedicated DMA Controller (DMAC e.g., 8237) transfers data directly between I/O device and Memory, bypassing CPU.
• Hardware: DMAC with registers: Address, Word Count, Control. Steals bus cycles via HOLD/HLDA (bus request/grant) or cycle stealing.
• Flow:
  1. CPU programs DMAC: source/destination address, count, direction (Read/Write), mode.
  2. CPU executes other program; DMAC waits for DREQ from device.
  3. DMAC asserts HOLD -> CPU releases buses (HLDA).
  4. DMAC generates addresses and controls MEMRD/MEMWR + IOR/IOW to move block, decrements count until 0, then sends Terminal Count interrupt to CPU.
• Modes: Burst (block) mode, Cycle Stealing (single word per time), Transparent mode.
• Advantages: Fastest, CPU free during transfer (except cycle stealing), ideal for bulk data.
• Disadvantages: Extra hardware controller, bus arbitration complexity, cache coherence issues.

Comparison Table:

Feature	Programmed I/O	Interrupt I/O	DMA
CPU Involvement	Full polling	Per word via ISR	Only init & end
Speed	Slowest	Medium	Fastest
Hardware Cost	Lowest	Moderate	Highest
CPU Utilization	Poor	Better	Best

In modern systems all three co-exist: polling for simple status, interrupts for events, DMA for bulk transfers (with bus mastering and I/O processors/channels).