Semiconductor Memory Organization

Semiconductor memory (SRAM/DRAM, ROM) is built from arrays of cells organized to provide $2^{n}$ words of $m$ bits each. Access is by address decoding.

1. Basic Cell

• SRAM cell: 6T flip-flop (bistable), no refresh, fast, large.
• DRAM cell: 1T + capacitor, needs refresh, dense.
• ROM cell: mask transistor.

2. Overall Organization Diagram

                         Address Bus A0..An-1
                              |
              +---------------v----------------+
              |      Row Decoder (n/2 bits)    |
              +---------------+----------------+
                              | word lines (rows)
               +--------------+--------------+
               |   Memory Cell Array         |
               |   ( 2^n rows x m columns )  |
               |   each row = one word       |
               +--------------+--------------+
                              | bit lines (columns)
              +---------------v----------------+
              | Column Decoder / MUX +         |
              | Sense Amplifiers + I/O Buffers|
              +---------------+----------------+
                              |
                          Data Bus D0..Dm-1
           CS (Chip Select), WE, OE , R/W

For $1024 \times 8$ chip: 10 address lines ($2^{10}=1024$), 8 data lines.

3. 2D Organization (Linear Decoding)

• One decoder decodes all $n$ bits to select 1 of $2^{n}$ word lines directly.
• Each word line enables $m$ cells forming a word.
• Simple but decoder size grows exponentially (for 64K, 16-to-65536 decoder impossible).

4. 2.5D / Coincident Decoding (Most common)

Address split into Row + Column: e.g., 10 bits -> 5 row + 5 column.

• Row decoder selects one of $32$ rows.
• Column decoder selects one of $32$ columns via column MUX.
• Only one cell at intersection selected per bit plane. Reduces decoder complexity.
• 3D organization: Adds bit plane selection.

Coincident decoding diagram:

 A0-A4 -> Row Decoder -> 32 word lines
 A5-A9 -> Column Decoder -> 32 column select
                Array 32x32 per bit plane x 8 planes = 1024x8

5. Building Larger Memories - Chip Organization

Using $k \times m$ chips to make $K \times M$ memory:

• Word expansion (depth): Use address MSB for chip select via decoder. e.g., Two $1K\times8$ -> $2K\times8$: A10 selects chip.
• Bit expansion (width): Parallel chips share address, each provides part of word. e.g., Two $1K\times4$ -> $1K\times8$: data buses combined.

Example: $4K\times8$ using $1K\times8$ chips:

 A0-A9 ----> all chips (address)
 A10-A11 -> 2-to-4 Decoder -> CS0,CS1,CS2,CS3 (one active)
 D0-D7 combined via tri-state buffers

6. Control Signals

• CS/CE: chip enable
• OE: output enable
• WE/R/W: read/write
• Tri-state buffers isolate bus when not selected.

This organization allows random access, high speed (SRAM 1-10ns, DRAM 50-70ns), and modular expansion by decoding.