Simple Hypothetical CPU Design

Consider a 16-bit accumulator-based or simple RISC CPU to illustrate principles (used by textbooks - similar to Mano's Basic Computer / Simple Hypothetical CPU).

1. Instruction Set (ISA) - 16-bit, 8-bit opcode + 8-bit address

Instruction	Opcode	Semantics
LDA addr	0001	AC <- M[addr]
STA addr	0010	M[addr] <- AC
ADD addr	0011	AC <- AC + M[addr]
SUB addr	0100	AC <- AC - M[addr]
AND addr	0101	AC <- AC & M[addr]
JMP addr	0110	PC <- addr
JZ addr	0111	if AC==0 PC <- addr
HLT	1111	Halt

Types: Memory-reference (LDA/STA), Arithmetic, Branch, Halt. Addressing: Direct (can extend to Immediate/Register).

2. Datapath

Registers: PC (8b), IR (16b: OP+ADDR), AR/MAR (8b), DR/MDR (16b), AC (16b), Status Z-flag.

Components:

• Memory (256x16b) - MAR selects, MDR buffers.
• ALU (16b) - inputs AC + MDR, ops ADD/SUB/AND, output -> AC, sets Z.
• Buses: Single internal bus or multiplexers connecting PC/IR/MAR/AC to memory/ALU.

Interconnections:

PC -> MUX -> MAR -> Memory -> MDR -\
IR(Addr) -> MAR                       -> MUX -> ALU -> AC
AC -> MDR -> Memory (store)           /
MDR -> IR (fetch)
PC+1 -> PC (incrementer)

3. Control Unit - Microcoded/Hardwired FSM

Fetch-Decode-Execute cycle (3-4 states):

• T0 Fetch: MAR <- PC; MDR <- M[MAR]; IR <- MDR; PC++
• T1 Decode: Decode IR[15:8] -> control signals; MAR <- IR[7:0]
• T2 Execute:
  • LDA: MDR <- M[MAR]; AC <- MDR
  • STA: MDR <- AC; M[MAR] <- MDR
  • ADD: MDR <- M[MAR]; AC <- AC+MDR
  • JMP: PC <- MAR
  • JZ: if Z PC <- MAR

Hardwired: State counter + PLA generates MemRead/Write, LoadPC/IR/MAR/MDR/AC, ALUop, BusSel.
Microprogrammed: Control memory 16 microwords storing same signals, MPC steps.

Diagram: Draw datapath with registers, ALU, memory, and control unit FSM outputting control lines.

This minimal CPU demonstrates Von-Neumann fetch-execute, single-bus bottleneck, and can be extended to multi-cycle with GPRs and pipeline.