Instruction Execution Cycle & x86 Features (7M)

A) Instruction Execution Cycle (Instruction Cycle)

Each instruction goes through sequence called Instruction Cycle controlled by CU.

Start -> Fetch -> Decode -> (Operand Fetch) -> Execute -> Writeback -> Interrupt Check -> Next

1. Fetch Cycle (IF):

• PC holds address of next instruction. MAR <- PC, PC++ (PC = PC + instruction_length). Memory read MDR <- Memory[MAR]; IR <- MDR. Fetch brings opcode + operands. Also increment IC.

2. Decode Cycle (ID):

• CU decodes opcode in IR via decoder, identifies instruction type, addressing mode, operand locations. Generates control signals. For microprogrammed CU, fetches micro-routine.

3. Operand Fetch / Effective Address Calculation:

• If instruction uses memory operand: Compute EA = Base + Index*Scale + Displacement using ALU. For x86: EA = EBX + ESI*4 + 0x10. Fetch operand Operand <- Memory[EA] or Register.

4. Execute Cycle (EX):

• ALU performs operation. Examples: ADD AX,BX => AX <- AX+BX sets FLAGS; JMP => PC <- target; LOAD => etc. Takes 1 to many cycles depending on complexity (mul/div = multiple cycles).

5. Store / Write Back:

• Result written to destination (Register or Memory). Memory[EA] <- AC or Reg <- Result. Flags updated (ZF,SF,CF,OF).

6. Interrupt Check:

• After each instruction, CU checks INTR, NMI. If asserted and enabled, save PC/PSW to stack and branch to ISR vector.

States:

Non-interrupt : FETCH -> INDIRECT (if indirect addr) -> EXECUTE
Interrupt     : ... EXECUTE -> INTERRUPT (save PC, PC <- vector)

Machine Cycle vs State: Each phase may take multiple clock states (T1-T4). e.g., 8086 MOV AX, [BX] = 4 clocks fetch + 6 clocks EA + memory read.

Example - ADD AX, [3000H] on hypothetical CPU:
T1: MAR<-PC, T2: MDR<-Mem, IR<-MDR, PC++
T3: Decode ADD, MAR<-3000H
T4: MDR<-Mem[3000H], TMP<-MDR
T5: AC<-AX+TMP, FLAGS update, AX<-AC

B) Key Features of x86 Architecture

x86 (8086 family, IA-32, x86-64) is CISC:

1. Register Organization: 8086: 4 GPR AX,BX,CX,DX (each 16b, divisible into AH/AL), 4 index/pointer SP,BP,SI,DI, 4 segment registers CS,DS,SS,ES, IP, FLAGS. IA-32 adds 32-bit EAX-EDI, ESI, EIP; x86-64 adds RAX-R15 (64-bit) + 16 XMM/YMM.

2. Segmentation & Memory Addressing: Real Mode: Physical addr = Segment*16 + Offset (20-bit via overlapping segments, 1MB). Protected Mode (80286+): Segment selector + descriptor table (GDT/LDT) giving base, limit, protection. Paging (80386+): 2-level paging to 4KB pages.

3. CISC Instruction Set: Variable length 1-15 bytes, many addressing modes (register, immediate, direct, register indirect, based, indexed, based-indexed with displacement), ~ 1000 opcodes (string: MOVS, REP). Complex instructions: REP MOVSB, ENTER.

4. Arithmetic Capabilities: Support for 8/16/32/64-bit, BCD (DAA/DAS), floating point via separate x87 FPU stack (ST0-ST7, 80-bit extended), later SSE/AVX for SIMD.

5. Modes of Operation:

   • Real Mode (8086 compatible)
   • Protected Mode (multitasking, privilege levels Ring 0-3, virtual memory)
   • Virtual 8086 Mode
   • System Management Mode (SMM)
   • Long Mode (x86-64, 64-bit)

6. Little-Endian: Lower address stores LSB.

7. Stack Support: Hardware stack via SS:SP with PUSH/POP, CALL/RET.

8. Interrupt Architecture: 256 vectored interrupts (0-255), INTR (maskable), NMI, Exception handling, IDT.

9. Backward Compatibility: All x86 generations run 8086 code; extensions via CPUID.

10. Extensions: MMX, SSE/SSE2/SSE4, AVX/AVX512 (SIMD for multimedia), Virtualization (VT-x), 64-bit extension (AMD64).

Comparison: Vs RISC: higher code density, but complex decode -> micro-ops translation to RISC-like internally (since Pentium Pro) for pipelined execution.