Addressing Modes with Examples (7M)

Definition: Addressing mode specifies rule for calculating Effective Address (EA) or operand location. Field A in instruction does not always equal EA; mode bits tell CPU how to interpret it.

General equation: EA = Base + Index * Scale + Displacement + PC-relative, value loaded accordingly.

Why x86 has many modes? To support arrays, pointers, stack, constants efficiently.

1. Immediate Mode

Operand itself in instruction. EA not needed.
Op = A

Example: MOV AX, 1234H ; ADD R1, #10 -> Instruction contains 00001010.
Use: Constants. Fast, no memory extra fetch beyond instruction.

2. Register Mode (Register Direct)

Operand in register R. EA is register ID, not memory.

Example: MOV AX, BX ; ADD R1, R2 => R1 = R1 + R2
Fastest (internal), used heavily in load-store architecture.

3. Direct / Absolute Mode

Instruction contains memory address A directly.

Example: LDA 2500H => AC = Mem[2500H] or MOV AX, [2000H]
EA = A

Need large address field (16/32 bit), inflexible if code relocates.

4. Indirect Mode

Address field points to memory location that contains EA. Extra memory access.

Example: MOV AX, [BX] where BX holds pointer? Actually register indirect below; true indirect: Instruction @ 100: 500; Mem[500] = 800 => operand = Mem[800]
Often: LDA @ 1000H -> Fetch address at 1000H, then fetch operand.
EA = Mem[A]

Rare directly due to extra fetch; used for pointers where pointer address known.

5. Register Indirect Mode

Pointer in register points to memory operand.

Example:

• MOV AX, [BX] => AX = Mem[BX] (BX=1000H => load from DS:1000H)
• LDA (R1) with R1=0x2000 => operand at 0x2000
EA = (R)

Powerful for array traversal: increment R per iteration.

6. Indexed Mode

EA = R + X where X is index register or immediate offset. Two variants:

• Based / Register + Displacement: MOV AX, [BX+10H] => EA = BX + 10H
• Indexed: MOV AX, [SI+20H]

Use: Array access A[i] = Base + i. Example: Array at 2000H, element 3 (2 bytes each): MOV SI, 6 ; MOV AX, [2000H+SI]

• Auto-increment / Auto-decrement (special): After access, R = R ± size. Example: MOV AX, [SI++] (68000 (A0)+) for stack/queue.

7. Base-Indexed Mode

Combination of two registers + displacement, favored by x86.

Example: MOV AX, [BX+SI+100H] or in 32-bit: MOV EAX, [EBX+ESI*4+8]

Base = BX/BP, Index = SI/DI. EA = Base + Index + Displacement

Use: 2D array A[i][j] where Base = row base, Index = col offset or accessing struct fields where BX = struct base, SI = field index.

8. Scaled Indexed Mode (x86)

EA = Base + Index*Scale + Disp where Scale = 1,2,4,8 (size of element).

Example: MOV EAX, [EBX + ECX*4 + 0x10] (ECX = array index, each element 4 bytes, 0x10 = header offset). Common in IA-32 SIB byte.

9. Relative / PC-Relative Mode

EA = PC + Displacement.

Example: JMP Label where Label at PC + 20 ; Branch BEQ -4 ; CALL PC+8

Use: Position-independent code (PIC), branches. Displacement is signed 8/16-bit.

10. Implied / Stack Mode

Operand implicitly implied (not in field). Stack pointer assumed.

Example: PUSH AX => SP--, Mem[SP]=AX; POP AX; CLC (Clear Carry - implied flag). Zero-address instruction ADD in stack machine pops two, pushes result.

11. Input/Output Mode

Special for I/O mapped: IN AL, 40H ; OUT 40H, AL (immediate port address or via DX).

Summary Table for Exam (Draw this)

Mode	Formula	Example (8086)	Effective Address
Immediate	Op=A	MOV AX, 5	-
Register	Op=R	MOV AX, BX	-
Direct	EA=A	MOV AX, [1000H]	1000H
Reg Indirect	EA=(R)	MOV AX, [BX]	(BX)
Indexed+Disp	EA=R+Disp	MOV AX, [SI+8]	SI+8
Based Indexed	EA=Base+Index	MOV AX, [BX+SI]	BX+SI
Based Indexed +Disp	EA=Base+Idx+Disp	MOV AX, [BX+SI+100H]	BX+SI+100H
Scaled	EA=Base+Idx*S+Disp	MOV EAX,[EBX+ECX*4]	EBX+ECX*4
Relative	EA=PC+Disp	JMP +20	PC+20

Selection Criteria: Instruction frequency, address space size, supporting high-level constructs (array, struct, pointer), code density. Modern RISC uses few modes (Register, Immediate, Indexed) for simpler decode; CISC offers many for compactness.