2024 question paper
COMPUTER ORGANIZATION & ARCHITECTURE
26 questions
Q1(a). What is the first step in the instruction execution cycle? (i) Decode (ii) Fetch (iii) Execute (iv) Store20242m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What is the first step in the instruction execution cycle?
(i) Decode
(ii) Fetch
(iii) Execute
(iv) StoreQ1(b). What is the advantage of carry look-ahead adders over ripple carry adders? i) Simplicity in design ii) Increased latency iii) Reduced power consumption iv) Faster addition by reducing carry propagation delay20242m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →What is the advantage of carry look-ahead adders over ripple carry adders?
i) Simplicity in design
ii) Increased latency
iii) Reduced power consumption
iv) Faster addition by reducing carry propagation delayQ1(c). Which type of control unit is faster but more difficult to modify? i) Hardwired Control Unit ii) Microprogrammed Control Unit iii) Cache Control Unit iv) Memory Management Unit20242m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Which type of control unit is faster but more difficult to modify?
i) Hardwired Control Unit
ii) Microprogrammed Control Unit
iii) Cache Control Unit
iv) Memory Management UnitQ1(d). Which of the following I/O transfer methods involves the CPU polling the device until data is read? i) DMA ii) Interrupt-driven I/O iii) Program-controlled I/O iv) Asynchronous I/O20242m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Which of the following I/O transfer methods involves the CPU polling the device until data is read?
i) DMA
ii) Interrupt-driven I/O
iii) Program-controlled I/O
iv) Asynchronous I/OQ1(e). What does a branch prediction mechanism in a CPU help reduce? a) Data hazards b) Control hazards c) Structural hazards d) Clock cycle delays20242m
Module 3: Pipelining
View this question on its own page →What does a branch prediction mechanism in a CPU help reduce?
a) Data hazards
b) Control hazards
c) Structural hazards
d) Clock cycle delaysQ1(f). Which of the following is *NOT* a type of parallel processor architecture? a) SIMD b) MIMD c) SISO d) Multi-core20242m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Which of the following is NOT a type of parallel processor architecture?
a) SIMD
b) MIMD
c) SISO
d) Multi-coreQ1(g). Which cache replacement algorithm removes the least recently used block. (i) FIFO (ii) LRU (iii) Random Replacement20242m
Module 4: Memory Organization
View this question on its own page →Which cache replacement algorithm removes the least recently used block.
(i) FIFO
(ii) LRU
(iii) Random ReplacementQ1(h). Which technique is used to handle data hazards in pipelining? a) Increasing memory size b) Instruction scheduling c) Parallel processing d) Increasing clock speed20242m
Module 3: Pipelining
View this question on its own page →Which technique is used to handle data hazards in pipelining?
a) Increasing memory size
b) Instruction scheduling
c) Parallel processing
d) Increasing clock speedQ1(i). __________________ Addressing mode directly specifies the operand within the instruction. i. Direct addressing ii. Indirect addressing iii. Immediate addressing iv. Indexed addressing20242m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →__________________ Addressing mode directly specifies the operand within the instruction.
i. Direct addressing
ii. Indirect addressing
iii. Immediate addressing
iv. Indexed addressingQ1(j). A computer with 32-bit wide data bus uses 1K, X, and 8 static RAM memory chips. What is the smallest memory that this computer has? a) 12K b) 10K c) 8K d) 16K e) 24K20242m
Module 4: Memory Organization
View this question on its own page →A computer with 32-bit wide data bus uses 1K, X, and 8 static RAM memory chips.
What is the smallest memory that this computer has?
a) 12K
b) 10K
c) 8K
d) 16K
e) 24KQ2(a). Describe the instruction execution cycle in a CPU. Explain some key features of the x86 architecture20247m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Describe the instruction execution cycle in a CPU. Explain some key features of the x86 architecture
Q2(b). Explain different addressing modes in a CPU with an example.20247m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain different addressing modes in a CPU with an example.
Q3(a). Explain the Addition and Subtraction Algorithm with the help of flowchart.20242m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Explain the Addition and Subtraction Algorithm with the help of flowchart.
Q3(b). What is a *carry-look ahead* adder? Draw the circuit of an 8-bit carry-look ahead adder using a *1-bit carry look ahead adder*.20247m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →What is a carry-look ahead adder? Draw the circuit of an 8-bit carry-look ahead adder using a 1-bit carry look ahead adder.
Q4(a). Explain different cache replacement algorithms used in memory management.20247m
Module 4: Memory Organization
View this question on its own page →Explain different cache replacement algorithms used in memory management.
Q4(b). What are the different types of Registers? With the diagram show how the basic computer register connected to a common Bus.20247m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →What are the different types of Registers? With the diagram show how the basic computer register connected to a common Bus.
Q5(a). Illustrate what are the challenges associated with concurrent access to memory in parallel processing?20247m
Module 4: Memory Organization
View this question on its own page →Illustrate what are the challenges associated with concurrent access to memory in parallel processing?
Q5(b). Describe different cache coherence protocols used in parallel processors.20247m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Describe different cache coherence protocols used in parallel processors.
Q6(a). A non-pipeline system takes 50 seconds to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10 seconds. Determine the speedup ratio of the pipeline for 100 tasks.20247m
Module 3: Pipelining
View this question on its own page →A non-pipeline system takes 50 seconds to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10 seconds. Determine the speedup ratio of the pipeline for 100 tasks.
Q6(b). What are pipeline hazards? Explain different types of hazards in pipelining.20247m
Module 3: Pipelining
View this question on its own page →What are pipeline hazards? Explain different types of hazards in pipelining.
Q7. Explain Booth's algorithm for multiplication and, with the help of flowchart, provide an example for its implementation.202414m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Explain Booth's algorithm for multiplication and, with the help of flowchart, provide an example for its implementation.
Q8. Describe different types of Input/Output transfers. Explain how data transfer takes place through DMA.202414m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Describe different types of Input/Output transfers. Explain how data transfer takes place through DMA.
Q9(a). Write short notes on any two of the following: a) RISC and CISC processor20247m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Write short notes on any two of the following:
a) RISC and CISC processorQ9(b). Write short notes on any two of the following: b) Fixed and Floating point representations20247m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Write short notes on any two of the following:
b) Fixed and Floating point representationsQ9(c). Write short notes on any two of the following: c) IO device interfaces20247m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Write short notes on any two of the following:
c) IO device interfacesQ9(d). Write short notes on any two of the following: d) Instruction Set Architecture20247m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Write short notes on any two of the following:
d) Instruction Set Architecture