Types of I/O Transfers

1. Programmed I/O: CPU polls status register, transfers one word at a time via IN/OUT instructions. Simple but CPU-bound.
2. Interrupt-Driven I/O: Device interrupts CPU when ready; CPU ISR transfers data. Avoids polling, still per-word CPU intervention.
3. Direct Memory Access (DMA): DMA controller transfers block of data directly between I/O device and memory without CPU per-word intervention. Most efficient for high-speed devices (disk, display, NIC). Also includes I/O Processor / Channel for more autonomous I/O.

DMA Data Transfer

Purpose: For $N$-word block, interrupt method needs $N$ interrupts; DMA needs only one interrupt per block.

DMA Controller Registers: Address Register (starting memory address), Word Count Register (number of words), Control Register (R/W, mode), Data Buffer.

Modes: Burst Mode (continuous transfer, CPU blocked), Cycle Stealing (DMA steals single bus cycle when CPU not using bus, interleaved), Transparent (only when CPU not using bus).

Sequence:

1. CPU initializes DMA: writes starting address $\rightarrow$ Address Reg, count $\rightarrow$ Count Reg, command $\rightarrow$ Control Reg (read/write, burst/cycle steal). CPU then executes other task.
2. Device requests DMA via DMA Request (DRQ).
3. DMA requests bus via Bus Request (BR) / HOLD to CPU.
4. CPU completes current bus cycle, relinquishes buses (places address/data/control in high-Z) and asserts Bus Grant (BG) / HLDA.
5. DMA becomes bus master: puts current memory address on address bus, asserts MEM RD/WR and I/O RD/WR, transfers one word between device and memory via its data buffer. Increments Address, decrements Count.
6. Repeat step 5 until Count $=0$ (cycle-stealing after each word or burst until zero).
7. On completion, DMA deasserts BR, asserts interrupt IRQ to CPU, sets done flag.
8. CPU ISR checks status, resumes.

During DMA transfer, address is supplied by DMA controller, not CPU. Bus arbitration logic (daisy chain or priority encoder) resolves competing DMA requests. Throughput $\approx$ memory speed for burst mode.