DMA Controller - Operation

Need: Programmed I/O and Interrupt I/O keep CPU busy for each word transfer. For high-speed devices (disk, ~1MB/s) CPU waste is large. DMA allows direct memory access without CPU intervention.

DMA Controller (DMAC) - e.g., 8237 sits between I/O and system bus. It is a slave to CPU for initialization and becomes master for transfer.

Architecture

• Address Register + Address Counter: Holds memory address, auto-increment/decrement.
• Word Count Register: Number of words to transfer.
• Control Register: Mode (read/write), burst/cycle-steal, etc.
• Data Buffer, Bus Control Logic, Interrupt Logic

Working Steps

1. Initialization (CPU as master): CPU writes via I/O instructions - starting address -> Address Reg, count -> WC Reg, control word -> Control Reg, I/O device address.
2. DMA Request: I/O device ready asserts DRQ (DMA Request) to DMAC.
3. Bus Request: DMAC asserts HOLD (or BR) to CPU.
4. Bus Grant: CPU finishes current bus cycle, tristates buses, asserts HLDA (BG).
5. Transfer: DMAC puts DACK to device and MEM_RD/WR, IO_RD/WR, controls buses, 1 word per DMA cycle. WC--, Address++.
   • Burst Mode: Holds bus until count=0
   • Cycle Steal: Releases bus after each word
   • Transparent: Only during CPU idle cycles
6. Termination: When WC = 0, DMAC asserts TC (Terminal Count), deasserts HOLD, interrupts CPU.

During transfer CPU is idle or can execute internal operations if buses not needed.

Example: Disk -> Memory (1KB)

CPU: MOV #1000, WC ; MOV #2000H, ADDR ; MOV #READ|BURST, CTRL
Disk controller seeks sector, asserts DRQ. DMAC acquires bus.
For 1000 cycles: DMAC: Address 2000H -> Address Bus, MEM_WR, Disk RD, word transferred, WC decremented. After 1000 words, interrupt CPU -> CPU verifies status.

Diagram: CPU - System Bus (Address/Data/Control) - DMAC - I/O Device, with HOLD/HLDA, DREQ/DACK, IOR/IOW, MEMR/MEMW.

Advantage: ~100x faster than programmed I/O, CPU free for other tasks.
Disadvantage: Cache coherence issue (stale data), bus contention.