DMA Controller

DMA controller is a dedicated hardware module that manages direct memory ↔ I/O transfers without CPU per-word involvement.

Block Diagram (textual):

 CPU ── Address/Data/Control Bus ─┬─ Main Memory
       ┌──────────────┐            ├─ DMA Controller ── I/O Device(s)
       │  CPU         │--HOLD/BR-->│ Address Reg (AR)   │
       │              │<--HLDA/BG--│ Count Reg (WC)     │-- DREQ/DRQ ← Device
       └──────────────┘            │ Control Reg        │-- DACK → Device
                                   │ Data Buffer        │-- IRQ → CPU
                                   │ Bus Arbiter        │
                                   └──────────────┘

Internal components: Address Register (current memory address, auto-incremented), Word Count Register (down-counter), Control/Status Register (R/W direction, transfer mode, enable, interrupt enable flag), Data Buffer/Latch, Bus Control Logic.

Use in System:

1. CPU programs DMA: loads AR = start address, WC = block size, Control = read/write, burst vs cycle-steal, channel priority. Enables DREQ mask.
2. CPU issues I/O command to peripheral, then continues program.

Operation:

• Peripheral asserts DRQ when ready for word.
• Controller asserts HOLD / Bus Request to CPU.
• CPU finishes current machine cycle, floats buses, asserts HLDA / Bus Grant.
• Controller drives address from AR onto address bus, generates MEM RD/WR and I/O RD/WR, transfers word via buffer. AR++, WC--.
• If WC≠0 and cycle-steal mode, releases HOLD for one cycle and reacquires next transfer; in burst mode holds bus until WC=0.
• When WC=0 → Terminal Count (TC) → controller deasserts HOLD, asserts Interrupt (IRQ) to CPU, sets DONE bit.

Modes: Single transfer, Block/Burst, Demand/Cascade (8237 A has 4 channels, chained). Advantage: For $n$-word block only one interrupt, bandwidth near memory bandwidth (~MB-GB/s) instead of ISR per word.

Multichannel controllers include priority resolver (fixed/rotating) for multiple devices arbitrating for DMA.