DMA Controller Initialization for DMA Data Transfer (14 Marks)

1. Introduction - What is DMA?

Direct Memory Access (DMA) allows I/O devices to transfer data directly to/from main memory without continuous CPU intervention. CPU only initializes the DMA controller, then DMA handles the transfer via cycle stealing / bus mastering, freeing CPU for other work.

Ideal for high-speed transfers: Disk, Network, Audio/Video, ADC.

Without DMA, CPU does programmed I/O - fetch each byte, poll status - very inefficient.

2. DMA System Block Diagram

                    SYSTEM BUS (Data, Address, Control)
     ┌─────────────────────────────────────────────────────────────────┐
     │                                                                 │
     │   ┌───────┐      ┌──────────────┐      ┌────────────┐  ┌──────┐ │
     └──►│  CPU  │◄────►│ DMA Controller│◄────►│   Memory   │  │ I/O  │ │
         └───┬───┘      │  (8237/82357) │      └────────────┘  │Device│ │
             │          │ ┌───────────┐ │                     └──────┘ │
             │  HOLD/HLDA│ │ Registers │ │                            │
             │◄─────────►│ │ - CAR     │ │                            │
             │          │ │ - CWCR    │ │  DREQ ──► Peripherals      │
             │          │ │ - Mode Reg│ │  DACK ◄── request/ack      │
             │          │ │ - Command │ │  HRQ/HLDA to CPU           │
             └──────────┴─┴───────────┴─┴──────────────────────────────┘

Detailed DMA Controller Inside:
┌─────────────────────────────────────────┐
│  DMA Controller (4 channels example)    │
│ ┌──────────────┐ ┌──────────────────┐   │
│ │ Channel Logic│ │ Address Register │   │
│ │ 0-3          │ │ (16/32 bit) CAR  │   │
│ ├──────────────┤ │ Count Register   │   │
│ │ Mode Register│ │ (CWCR)           │   │
│ │ Command Reg  │ │ Data Buffer      │   │
│ │ Status Reg   │ │ Timing & Control │   │
│ │ Request Reg  │ │ Priority Encoder │   │
│ └──────────────┘ └──────────────────┘   │
└─────────────────────────────────────────┘

Signals: HRQ (Hold Request) -> CPU HOLD, HLDA <- CPU, DREQ (DMA Request from I/O), DACK (DMA Acknowledge), MEMR/MEMW, IOR/IOW, AEN (Address Enable), ADSTB

Connections: DMA sits between CPU, Memory and I/O. When idle, bus controlled by CPU. When active, DMA becomes bus master.

3. DMA Registers to be Initialized

Before any transfer, CPU (as program) must program following internal registers of DMA via I/O mapped writes (using CS, A0-A3, IOW):

Register	Purpose	Example
Starting Address Register (CAR)	Base address in memory where transfer starts	0x2000
Count Register (CWCR / Terminal Count)	Number of bytes/words to transfer -1	N-1 (e.g., 1023 for 1KB)
Mode Register	Transfer type: Read/Write/Verify, Auto-init, Address inc/dec, Demand/Single/Block	0x58 = Block, Inc, Write
Command Register	Controller enable/disable, priority (fixed/rotating), DREQ sense, memory-to-memory	0x00
Mask Register	Mask/unmask channel, enable DREQ	Clear mask
Request Register	Software request (for M-M transfer)

For 8237A: 4 channels, each 16-bit address + 16-bit count + 6-bit mode.

4. Step-by-Step Initialization Sequence

Assumption: Want to transfer 1KB from Disk (I/O port) to Memory address 0x20000 using Channel-1 Burst/Block mode.

Phase A: CPU Preparation

1. CPU executes setup routine with interrupts disabled (or handling).
2. CPU checks DMA idle - reads Status Register - ensure no ongoing transfer, channel not masked busy.

Phase B: Programming DMA (CPU as master, DMA as slave)

CPU writes via I/O instructions (OUT) to DMA port addresses:

Step 1: Send starting address

OUT CommandReg, 0x0C (clear First/Last flip-flop for 8237)
OUT AddressReg Ch1, Low Byte (0x00)
OUT AddressReg Ch1, High Byte (0x00)  -> also Page Register for A16-A23 if 24-bit (0x02)

Step 2: Send word count (N-1)

OUT CountReg Ch1, Low Byte (0xFF)  // 1024-1 = 1023 = 0x03FF
OUT CountReg Ch1, High Byte (0x03)

Step 3: Program Mode Register for Channel 1

Mode byte: [D7-D6=01][D5=0][D4=0][D3-D2=01][D1-D0=01]
           Channel select+ Transfer type (Write: I/O->Mem) + Auto-init 0 + Addr inc + Demand/Block
OUT ModeReg, 0x58

Step 4: Program Command Register

Bits: Fixed priority, Late write, DREQ active high, DACK active low
OUT CommandReg, 0x00

Step 5: Unmask Channel

OUT MaskReg, 0x01 (bit0=1 unmasks Ch1) or 0x01 -> using single mask: 0x01
Actually 8237 single mask: bit2=0 -> unmask, bits1-0=01 -> Ch1 => 0x01

Phase C: Initiate Transfer

3. I/O device enabled: Disk controller programmed via its own registers (sector, drive) to be ready.
4. Device asserts DREQ1 (when data ready)
5. DMA asserts HRQ -> CPU responds HLDA -> CPU tristates buses (floats Address/Data/Control) -> DMA asserts AEN=1, takes bus mastership, signals HLDA to device?
6. DMA outputs memory address on bus from CAR, asserts DACK1 to device, MEMW + IOR (for I/O->Memory) or MEMR+IOW (Memory->I/O). Data moves directly without CPU register.
7. After each byte: CAR increment/decrement, Count decrement. Bus stays with DMA in Block mode until TC, else released per byte in Single mode.
8. When Count = 0xFFFF (roll-over) => Terminal Count (TC) reached, DMA pulses EOP*, raises interrupt TC, deasserts HRQ, releases bus, sets Status bit.

Phase D: Termination & CPU Resumes

• Status Register can be polled / interrupt: CPU ISR reads status, checks TC for channel, handling completion.
• If Auto-initialization set, registers reload original values for next block; else channel masked.
• CPU resumes: HLDA deasserted, clears AEN, regains bus.

5. Initialization Flow Chart

CPU Program Start
      │
      ▼
Disable DMA? Check Status Idle
      │
      ▼
Write Base Address → CAR + Page Reg
      │
      ▼
Write Block Length → CWCR
      │
      ▼
Write Mode Reg (DIR, TYPE, MODE)
      │
      ▼
Write Command Reg
      │
      ▼
Unmask Channel (Enable DREQ)
      │
      ▼
Program I/O Device registers
      │
      ▼
Device asserts DREQ → DMA HRQ → CPU HLDA
      │
      ▼
DMA Bus Master → Transfer (Cycle Steal/Block)
      │
      ▼
TC? → EOP/Interrupt → CPU ISR → Done

6. Transfer Modes Programmed During Init

• Single Mode: One byte per DREQ, release bus - fair to CPU
• Block/Burst Mode: Entire block in one HRQ - fastest
• Demand Mode: Until DREQ deasserted - e.g. disk not ready
• Cascade: Connect multiple controllers

7. Example 8086 + 8237 Connection

CPU 8237 pins: CLK, RESET, CS*, IOR*, IOW*, A0-A3, D0-D7 to bus via latch 8282/8286. HRQ to 8086 HOLD, HLDA from 8086, DREQ0-3 from peripherals, DACK0-3 back, AEN to bus controller 8288 to disable CPU addresses, ADSTB to latch high address.

8. Importance / Advantages

• CPU free for computation during transfer → ~10-100x faster for bulk data
• Near memory speed transfer (limited by memory cycle + bus)
• Essential for modern systems - integrated DMA in PCI/PCIe bus mastering, not just 8237.

Exam Tip: Always draw block diagram + label registers + stepwise OUT sequence. For 14 marks, include both diagram, table of registers, sequence code, and timing (HRQ/HLDA handshaking).