Flynn's Classification (1966) – based on number of Instruction streams and Data streams

Streams = sequence of instructions / data operated by CPU.

	Single Data (SD)	Multiple Data (MD)
Single Instruction (SI)	SISD	SIMD
Multiple Instruction (MI)	MISD	MIMD

1. SISD – Single Instruction Single Data

• One control unit, one ALU, one data stream. Sequential execution (von Neumann).
• Eg: Uniprocessor 8086, RISC, single-core CPU.
• Instruction: $I_1 \rightarrow D_1$ then $I_2 \rightarrow D_2$ …
• No parallelism. Performance via pipelining.

   CU ---> PU ---> Memory
    1      1      1

2. SIMD – Single Instruction Multiple Data

• One instruction stream broadcast to many processing elements (PEs), each with own data.
• Array / Vector processors, GPU.
• Eg: ILLIAC-IV, Vector supercomputers, MMX/SSE, GPU warps.
• Operation: One opcode ADD executes on vectors $A[0..n]+B[0..n]$ in lockstep.

         CU
          |
   +------+------+------+
   PE     PE     PE     PE
   D1     D2     D3     D4

• Exploits data parallelism, high throughput for multimedia, matrix ops. Requires synchronous control.

3. MISD – Multiple Instruction Single Data

• Many instructions operate on same data stream. Rare / theoretical.
• Eg: Systolic arrays, fault-tolerant systems where same data through different algorithms ($N$-version programming), pipeline MISD interpretation: successive stages apply different operations on same data flowing through.
• No commercial general MISD.

  CU1 ---> PU1 --\
  CU2 ---> PU2 ---> same Data stream (pipelined)
  CU3 ---> PU3 --/

4. MIMD – Multiple Instruction Multiple Data

• Multiple autonomous processors each with own instruction and data stream. Most general, multiprocessors / multicomputers.
• Two subclasses:
  • Tightly coupled / Shared memory (SMP, multi-core): All CPUs share common RAM via bus/crossbar. Eg: Intel i7 quad-core, Xeon.
  • Loosely coupled / Distributed memory (message passing): Each node has private memory, communicates via network. Eg: Clusters, supercomputers (Beowulf).

  CU1->PU1->M1 \
  CU2->PU2->M2 ---> Interconnection Network
  CU3->PU3->M3 /

• Exploits task parallelism, true concurrency, scales (but needs synchronization, coherence).

Summary Table

Type	#CU	#PU	Use	Example	Parallelism
SISD	1	1	General	8086, ARM single	ILP only
SIMD	1	N	Vector	GPU, AVX	Data
MISD	N	1	Special	Systolic, fault-tolerant	Rare
MIMD	N	N	General parallel	Multi-core, Cluster	Task/Data

Extended taxonomies: SPMD (Single Program Multiple Data – subset of MIMD), MPMD. Modern machines are hybrid: MIMD of SIMD cores (multi-core GPU).

Diagram: All 4 types [SISD = single lane, SIMD = single instruction fan-out, MISD = multiple instr single data pipeline, MIMD = multiple independent lanes].