Main Structural Components of a Computer (7M)

Derived from Von Neumann model (Stallings). Four top-level components interconnected via System Bus.

                +-------------------+
                |   System Bus      |
                | A (Address) D (Data) C (Control) |
                +--+-----+------+---+
                   |     |      |
        +----------+ +---+----+ +--+----------+
        |   CPU    | | Memory | | I/O System  |
        |Processor | |        | |Module/Device|
        +----------++----+-----+ +-------------+
               |          |            |
        (Control, ALU, Registers)

1. Central Processing Unit (CPU) - Brain

• Function: Fetches instructions, decodes, executes, controls entire system.
• Sub-components:
  • ALU (Arithmetic Logic Unit): Performs arithmetic (ADD, SUB, MUL) and logical (AND, OR, NOT, SHIFT). Operates on registers.
  • Control Unit (CU): Generates timing & control signals (micro-operations) to coordinate fetch-decode-execute. Hardwired or Microprogrammed.
  • Registers: Very fast internal storage - PC (Program Counter), IR (Instruction Register), MAR/MDR (Memory Address/Data Registers), GPRs, PSW/FLAGS, SP.
  • Internal Bus: Connects CU-ALU-Registers.

CPU performs Fetch Cycle (MAR <- PC, MDR <- Memory, IR <- MDR, PC++) and Execute Cycle.

2. Main Memory - Storage for Program & Data

• Function: Stores instructions & data temporarily while program runs. Byte-addressable, random access.
• Types: RAM (Volatile, read/write) - DRAM/SRAM for main memory; ROM (Non-volatile) - BIOS, bootstrap.
• Organization: Address space 2^n locations, n = address bus width (e.g., 32-bit CPU -> 4GB). Memory hierarchy includes Cache (SRAM, L1/L2/L3 between CPU & RAM) to bridge speed gap.
• Interface: Address Bus selects location, Data Bus carries data, Control (MEMR/MEMW) signals read/write. Access time ~ 50-100 ns vs CPU cycle ~ 1 ns -> cache needed.

3. I/O System (Input / Output) - Interface to External World

• Function: Transfers data between computer and peripherals / outside. Also called I/O Module / I/O Subsystem.
• Examples: Keyboard, Mouse, Display, Disk, Network card, Printer, Sensors.
• I/O Module Functions: Control & timing, CPU communication (decode address, data buffering), device communication, error detection.
• Techniques: Programmed I/O, Interrupt-driven I/O, DMA (direct memory access). Includes ports, device controllers, bus adapters.

4. System Bus - Communication Highway

• Function: Set of shared communication lines interconnecting CPU, Memory, I/O. Uses bus protocols/arbitration.

Three buses (can be multiplexed):

• Address Bus (Unidirectional, CPU -> Memory/I/O): Carries address k-bits to select one of 2^k locations. With 32-bit bus => 4GB.
• Data Bus (Bidirectional): Carries data/instruction word (8/16/32/64-bit) - width determines word size.
• Control Bus (Mixed): Carries control signals - MEMR*, MEMW*, IOR*, IOW*, CLK, RESET, READY, INTR, HOLD/HLDA, INTA*.

In single-bus structure, only one transfer at a time; arbitration needed (centralized 8289 or distributed).

Operation Cycle Example: CPU places address on Address Bus -> asserts MEMR* on Control Bus -> Memory puts data on Data Bus -> CPU latches via MDR.

Supplementary Interconnections:
Some texts list Interconnection Structure as 5th view, but exam expects 4. Mention that performance depends on bus width/speed (bandwidth = data_width * clock_rate).

For diagram: Draw central System Bus as three lines linking four blocks; inside CPU expand to CU+ALU+Registers; show I/O module between bus and peripheral.