Design and Logic of a Microprogram Sequence (7M)

1. Microprogrammed Control Unit Basics

Instead of hardwired logic, Control Unit stores microinstructions (control words) in Control Memory (CM) / microstore (ROM/Flash). Each microinstruction is a set of control signals (PCout, MARin, Read etc.). A macro-instruction (e.g., ADD) is executed as a sequence of microinstructions - called microprogram.

Wilkes (1951) proposed this concept.

Example: Fetch phase micro-sequence

T1: PCout, MARin, Read, Select4, Yin, WMFC
T2: MDRout, IRin, PC+4

2. Microinstruction Format

• Control field (CW): n bits, one per control line (horizontal) or encoded (vertical).
• Next Address field: Address of next microinstruction in CM.
• Branch/Sequencing field: Condition select + branch control.

Two types control encoding:

• Horizontal: 1 bit per signal (wide, fast, e.g., 40-60 bit microinstruction)
• Vertical: Encoded fields (narrow, slow, needs decoder)
• Nanoprogramming: Two-level.

3. Design of Microprogram Sequence Logic - Next Microaddress Generation

After executing current microinstruction at address uPC, how to find next uPC ?

Three techniques:

a) Sequential + Explicit Address:
Next address supplied in current microinstruction. Simple but wastes bits if many sequential steps.

uPC_next = Addr field of current microinstruction

b) Incremental uPC + Branch (Most common):
Use microprogram counter uPC that increments by 1 by default; if branch condition true, load address from current microinstruction.

if (Branch = 0)   uPC = uPC + 1
else if (Cond true) uPC = BranchAddress
else              uPC = uPC + 1

Uses uPC register + incrementer + MUX. Condition flags: ZERO, CARRY, OPCODE bits, INTERRUPT, BUSY.

c) Mapping via Opcode (Dispatch):
After fetch & decode, opcode bits in IR map to starting address of corresponding microprogram via mapping ROM / decoder.

Start Address = Mapping(IR[opcode])
E.g., ADD (opcode 0010) -> µaddr 0x10, SUB -> 0x18.

Implemented as: High bits from table + low bits from opcode. Often a Dispatch ROM does µAddr = Base + opcode * offset.

d) Combinations: Two-phase sequencing

Modern microprogrammed CU does:

1. Fetch sequence (fixed at µaddr 0)
2. Decode/dispatch (branch on IR opcode)
3. Execute sequence for that opcode
4. Branch back to fetch or handle indirect addressing / interrupt.

4. Logic Diagram (Next Address Generator)

         +-----+  Condition codes (FLAGS, IR bits)
         | MUX |<-----------------+
         +-----+                  |
            ^  +-------------+   +-----------+
            |  | Branch Addr |   | Condition |
            |  | from µIR    |   | Select    |
            |  +-------------+   +-----------+
+-----+ +---+----+ +--------+    +----------+   +----+
| uPC |->| CM   |->| µIR    |---->| Next Addr|-->|uPC |
| Reg |<-| (ROM)|  | (hold) |    | Logic    |   |    |
+-----+ +---+----+ +--------+    +----------+   +----+
   ^        |         | control signals ---------> to CPU datapath
   +--------+ Incrementer (uPC+1) ---------------+

Components: Control Memory (512 x 36 bit typical), Control Address Register (CAR/uPC), Control Data/Register (CDR/µIR), Next-address logic (incrementer + branch MUX + mapping PROM).

5. Example Microprogram Sequence for ADD R1, (R2)

Assume instruction: ADD R1, [R2] (R1 = R1 + Mem[R2])

µAddr : Microoperation Comment
0 : PCout, MARin, Read, WMFC Fetch opcode
1 : MDRout, IRin, PC++ Load IR
2 : R2out, MARin, Read Use R2 as address
3 : MDRout, Yin, WMFC Load operand to Y
4 : R1out, SelectY, Add, Zin ALU ADD
5 : Zout, R1in, END Write back, return to fetch

Dispatch after µaddr1: If opcode = ADD, µPC = 2, if BRA then goto branch routine, etc.

6. Design Steps (for exam)

1. List datapath control signals needed (Register in/out, ALU function, Memory Read/Write, PC inc).
2. Write micro-operation sequences for each macro instruction (fetch-decode-execute).
3. Encode signals into µinstruction control field (horizontal/vertical choice) - consider control word width vs decode delay.
4. Determine sequencing needed: sequential flow, conditional branch on flags/ opcode, subroutine calls (e.g., for interrupt handling, CALL micro-subroutine with µ-stack).
5. Choose next-address logic implementation: plain counter vs mapping ROM; assign CM addresses; generate mapping function.
6. Optimize with field encoding, nanostore, or writable control memory (WCS) for vertical microprogramming to reduce size.

Advantages: Flexible (change microprogram to change instruction set), easier debugging, supports complex CISC (IBM 360, 68000, x86). Disadvantage: Slower than hardwired due to CM access (1 cycle extra); modern RISC uses hardwired, but x86 internally translates CISC to RISC µops via microcode.

Diagram to draw: Microprogrammed CU block with CM, CAR, CDR, mapping logic, and next-address generation MUX branching back.