Hypothetical: Instruction = 32 bits = 8 bits opcode + 24 bits address/immediate.

(a) Maximum Directly Addressable Memory Capacity

Direct field = $32-8 = 24$ bits.

If byte-addressable: $Capacity = 2^{24}$ bytes $=16,777,216$ B $=16$ MB.

If word-addressable (32-bit word =4B): $2^{24}$ words $= 2^{24}\times4 = 2^{26}$ B $=64$ MB, i.e. $4M$ words.

Note: If microprocessor internally has full 32-bit address bus, theoretical max = $2^{32}$ B $=4$ GB, but with given format without indirect/indexing you can only encode 24-bit direct address $\Rightarrow$ only $16$ MB directly without using indirect or paging.

(b) Impact of Bus Width on Speed

Assume memory and CPU are 32-bit, but buses narrower:

i) 32-bit address bus, 16-bit data bus

• Address bus 32-bit $\Rightarrow$ can address full $2^{32}=4$ GB.
• Data bus 16-bit $\Rightarrow$ each 32-bit instruction or operand needs 2 bus cycles to fetch/transfer (16 bits per cycle).
  • e.g. Instruction fetch: $T_{fetch}=2\times T_{bus}$ vs $1\times$ with 32-bit data bus.
  • Data read/write of 32-bit word also 2 cycles. Bus bandwidth halved: $BW = 16$ bits/cycle vs $32$.
  • Needs two memory accesses, causes wait states, effective CPI increases.
  • Still functionally correct, but speed roughly ~50% for memory-intensive code + extra control logic (byte assembly, multiplexing).

ii) 16-bit address bus, 16-bit data bus

• Address 16-bit $\Rightarrow$ directly addressable = $2^{16}=64$ KB only! Massive limitation.
  • To access beyond 64KB need banking, segment registers, page registers, or multiplexed address (like 8086 with 20-bit via segment:offset) – adds software/hardware overhead and slowdown.
  • Cannot use full 32-bit address field; higher bits must be latched in two cycles (address multiplexing) or ignored.
• Data 16-bit $\Rightarrow$ same 2-cycle fetch as case (i).
• Overall: Much slower than (i) + severely limited memory. Requires extra bus cycles to send full 32-bit address (send low 16 then high 16) if attempting to address 4GB, effectively 2 address cycles + 2 data cycles per access. System speed degraded by $> 2\times$ and programmability restricted.

Summary: Widening address bus increases address space; widening data bus increases throughput. Halving data bus doubles memory cycles. Halving address bus collapses address space.

(c) Bits needed for PC and IR

• Instruction Register (IR): Must hold full instruction $=32$ bits (8 opcode +24 operand). So $IR=32$ bits.
• Program Counter (PC): Must hold address of next instruction.
  • If holding direct field only: $24$ bits (to address $16$ MB).
  • If holding full memory address (32-bit address bus): $32$ bits to address full $4$ GB, even though instruction can only encode 24 bits directly (rest via indirect).
  • Practical design: $PC=32$ bits, $IR=32$ bits. For byte-addressable with word-aligned instructions (4B), PC increments by 4.

Exam answer: $IR=32$ bits, $PC=24$ bits minimum ($32$ bits for full 4GB system).