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COMPUTER ORGANIZATION & ARCHITECTUREHow many ROM chips are required to produce a memory capacity of 4096 bytes? How many address lines are required to access the 4096 bytes? How many of these addresses will be common to all these chips?201714mCOMPUTER ORGANIZATION & ARCHITECTUREA computer with 32-bit wide data bus uses 1K, X, and 8 static RAM memory chips. What is the smallest memory that this computer has? a) 12K b) 10K c) 8K d) 16K e) 24K20242mCOMPUTER ORGANIZATION & ARCHITECTURERegisters R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the effective address of the memory operand in each of the following instructions? - (i) Load 20(R1), R5 - (ii) Add –(R2), R520142mCOMPUTER ORGANIZATION & ARCHITECTUREExplain register reference and memory reference instructions in detail with suitable examples.20197m
Previous(b) Discuss the design and logic of a microprogram sequence.NextA set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the cache structure and show how the processor’s addresses are interpreted.