Microprogram Sequencer for Control Memory

Microprogrammed control unit uses Control Memory (ROM) to store microinstructions instead of hardwired logic. The microprogram sequencer generates the next address in control memory.

Block Diagram

                     +-------------------+
                     | Control Memory    |
                     | (ROM) micro-      |----> Control Word
                     | instructions      |      (to datapath)
                     +---------+---------+
                               |
                        +------v------+
                        |  Control    |
                        | Data Register|
                        |   (CDR) /   |
                        | Pipeline Reg|
                        +------+------+
                               |
+--------------------------------------------------------------+
|                    Microprogram Sequencer                     |
|                                                               |
|  External                                    +----------------+ |
|  Inputs ----> +----------------+             |  Multiplexer   | |
|  (I, Flags,  |  Mapping Logic |-----------> |  (MUX)         | |
|   IR op)     |  (Address gen) |             |                | |
|              +----------------+             |                | |
|                                            |   +----------+ | |
|  +------+    +------------+    +-------+   +-->| Control  | | |
|  | SBR  |<-->| CAR (µPC)  |<---| Inc.  |<------| Address  | | |
|  |Stack |    | Address Reg|    | +1    |       | Register | | |
|  |      |    +------------+    +-------+       |  (CAR)   | | |
|  +------+         ^                             +----------+ | |
|     ^             |                                           | |
|     |        +----+------+                                    | |
|     +--------|  MUX Select|<-- Flags (S,Z,C) + CDR bits (cond)| |
|              |  Logic    |                                    | |
|              +-----------+                                    | |
+--------------------------------------------------------------+
         |                           ^
         |                           |
      CALL/RET              Branch Address from CDR

Simplified alternative view (standard textbook):

                +-------------------+
  MUX Select -->|  MUX (4:1)        |---> CAR ---> Control Memory ---> CDR
                |  0: CAR+1         |     (µPC)     Address
                |  1: Branch Addr   |
                |  2: Mapping       |
                |  3: SBR Top       |
                +-------------------+
                    ^      ^
                    |      +-- Mapping Logic <- IR (opcode)
                    |
               SBR (Stack for CALL/RET) <-- CDR condition bits + Flags

Components and Explanation

1. Control Address Register (CAR) / µPC: Holds address of next microinstruction to fetch. Like PC for microprogram.

2. Control Data Register (CDR) / Pipeline Register: Holds current microinstruction fetched from control memory. Its fields provide:

   • Control signals for datapath
   • Next-address information (branch address, condition select bits)
   • Condition to test

3. Incrementer (+1): Generates CAR+1 for sequential execution (next microinstruction).

4. Multiplexer (MUX): Selects one of several next-address sources:

   • Incrementer (CAR+1) - for sequential continuation
   • Branch address from CDR (for conditional/unconditional branch in microprogram)
   • Mapping logic output - maps macro opcode (from IR) to starting micro-routine address
   • SBR Top - return address from subroutine stack

5. Mapping Logic: Combinational circuit that converts instruction opcode (e.g., ADD, BRA) into starting address in control memory where its micro-routine is stored. Avoids sequential search.

6. SBR - Subroutine Register (Stack): Small LIFO stack to save/restore CAR during microprogram subroutine calls (CALL pushes CAR+1, RET pops to CAR). Needed for reusable micro-subroutines (e.g., fetch).

7. MUX Select Logic: Determines MUX selection based on:

   • Conditional bits in current microinstruction (e.g., JCC field)
   • Status flags (Zero, Carry, Sign) and external inputs
   • Unconditional branch bit

Operation Sequence

1. CAR addresses control memory -> microinstruction loaded into CDR.
2. Control field of CDR drives datapath; next-address field goes to sequencer.
3. Incrementer computes CAR+1.
4. Select logic evaluates condition flags + CDR condition bits -> chooses MUX input.
5. Chosen address loaded into CAR at next clock.
6. If microinstruction is CALL, current CAR+1 pushed to SBR; if RET, popped.

This enables conditional branching, subroutine calls, and opcode mapping inside control memory, making control unit flexible - only ROM contents need change to modify instruction set.