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Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

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What do you understand by hardwired control? Give various methods to design a hardwired control unit. Describe any one with a suitable example.

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Solution - Hardwired Control

What is Hardwired Control?
Hardwired control is a method of control unit design where control signals are generated by fixed combinational logic circuits (gates, encoders, decoders, flip-flops) as Boolean functions of input variables: Opcode (II), Timing signals (TT), Flags (FF), and Clock. No control memory is used. Each control signal Ck=f(I,T,F)C_k = f(I,T,F). It is fast but inflexible - any change requires physical rewiring.

Various Methods to Design Hardwired Control Unit:

  1. State Table / Classical Method (Sequence Table + Logic)
  2. Delay Element (Switching Delay) Method
  3. Sequence Counter (Counter) Method - Most Popular
  4. PLA (Programmable Logic Array) Method

Describe in Detail: Sequence Counter Method (with example):

This is the most widely used textbook method.

Hardware:

  • A kk-bit Sequence Counter (SC) / ring counter that counts clock pulses and generates timing states T0,T1,T2...Tn−1T_0,T_1,T_2...T_{n-1} cyclically. Usually decoded to one-hot.
  • An Instruction Decoder that decodes IR-opcode into D0...Dm−1D_0...D_{m-1} lines.
  • Combinational Encoder (AND-OR network / PLA) to generate control signals.
  • Control logic also uses Flags and mode bits.

Working - Example: 3-instruction CPU (LDA, ADD, BUN):
Suppose SC counts T0T_0 to T3T_3. Control signals are:

  • Fetch (common to all):
    T0:PCout→ART_0: PC_{out} \to AR
    T1:M[AR]→DR,PC+1→PCT_1: M[AR] \to DR, PC+1 \to PC
    T2:DR→IR,DecodeT_2: DR \to IR, Decode
  • Execute depends on DiD_i:
    D0T3:M[IRaddr]→DRD_0 T_3: M[IR_{addr}] \to DR (LDA)
    D0T4:DR→ACD_0 T_4: DR \to AC
    D1T3:M[IRaddr]→DRD_1 T_3: M[IR_{addr}] \to DR (ADD)
    D1T4:AC+DR→ACD_1 T_4: AC+DR \to AC
    D2T3:IRaddr→PCD_2 T_3: IR_{addr} \to PC (BUN)

Boolean expression: ACload=D0T4+D1T4AC_{load} = D_0 T_4 + D_1 T_4

Sequence:

  1. Initially SC=0SC=0. At T0T_0 fetch step.
  2. After each clock, SC increments; decoder selects instruction-specific path.
  3. At TlastT_{last} SC is cleared to 0 for next fetch, END signal generated.

Advantages of Counter Method: Systematic, easy to understand timing.
Disadvantage: Many gates, counter delay.

Other methods briefly:

  • Delay Element: Chain of delay elements propagates control pulse sequentially to generate TiT_i without counter - simple but delay not precise.
  • PLA Method: All combinational logic fused into one PLA - compact, used in modern RISC hardwired CU for high speed.

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