Hardwired vs Microprogrammed Control Unit

Aspect	Hardwired Control	Microprogrammed Control
Principle	Control signals generated by combinational circuit (logic gates, encoder/decoder, sequence counter SC, flip-flops). Fixed wiring.	Control signals generated by microprogram stored in Control Memory (ROM). Each microinstruction bit = one control signal; execution = fetching microinstructions.
Structure	Gates + Decoder (IR opcode -> D0-D7) + Timing $T_0..T_{15}$ from SC + Flip-flops (E, I) + Encoder to generate $S_2S_1S_0$, $LD_{AC}$ etc.	Control Address Register (CAR), Control Data Register (CDR), Control Memory (256x20 bits), Next-address logic / Sequencer, Control Buffer Register.
Storage	No stored program. Combinational logic.	Microprogram in ROM/RAM (firmware). $n$ microinstructions per machine instruction.
Speed	Fast (gate delay only) ~ 1-2 gate levels. Ideal for RISC, pipelined.	Slower (control memory access each microcycle, ~1 memory fetch per microinstruction)
Flexibility	Inflexible - to change instruction set need to redesign hardware/wiring. Complex to modify.	Flexible - change by updating microcode ROM; add new instruction by adding microroutine. Easy to support CISC complex instructions.
Design Cost	Complex design for many instructions (many states, hard to debug). But cheap hardware for simple ISAs.	Easier design: write microprogram akin to programming. Modular.
Complexity handling	Becomes unwieldy when instructions > ~50, addressing modes many (state explosion).	Handles complex instructions (MUL, interrupt) easily - just longer microroutine. Used in CISC (IBM 360, VAX, 68000).
Control signals	Generated as Boolean equations: e.g., $LD_{AR}= D_4T_0 + D_5T_4$	Each bit of microinstruction directly drives signal: $F_1F_2F_3, D_7..D_0$ etc.
Modification	Requires hardware change (ECN).	Can be patched via writable control store (WCS) - firmware update.
Example	RISC processors (MIPS, ARM), old 8085 hardwired, Mano basic computer simplified hardwired version.	Historical: IBM System/360, Intel microcode for x86 CISC, modern x86 decodes complex instructions to micro-ops from microcode ROM.
Control memory size	None	Need $2^k \times$ width ROM; control throughput is fetch-decode of microinstructions (horizontal vs vertical microcode).
Techniques	Sequence counter + decoder; one-hot, PLA	Horizontal (many bits per microinst, parallel) vs Vertical (encoded fields, compact) ; Wilkes model.

Diagram Analogy

• Hardwired: IR,T,I,SC -> Combinational Logic (PLA) -> 30 control lines
• Microprogrammed: IR -> Map -> CAR -> Control Memory -> CDR -> control lines; CDR.next_addr -> CAR

Horizontal vs Vertical within Microprogrammed

• Horizontal: 40-60 bits, each bit one signal - high parallelism, fast but large ROM.
• Vertical: 16-20 bits encoded, needs decoder, compact but slower.

Modern hybrid: RISC core hardwired for simple ops + microcode ROM for complex x86 instructions translated to micro-ops (e.g., Intel/AMD).

Conclusion: Use Hardwired when speed is critical and instruction set simple/small; use Microprogrammed when instruction set is complex/variable and design flexibility/upgradeability matters.