Fetch-Decode-Execute Cycle (Instruction Cycle)

Every instruction goes through this cycle, driven by clock and controlled by Control Unit + SC (Sequence Counter). Also called Fetch-Decode-Execute (FDE) or Instruction Cycle.

1. Fetch Phase

• PC holds address of next instruction.
• AR <- PC
• IR <- M[AR] (Memory Read), PC <- PC+1 (point to next)
• $T_0: AR \leftarrow PC$, $T_1: IR \leftarrow M[AR], PC \leftarrow PC+1$
• Instruction now in IR: bits 0-11 = opcode+mode, 12-...= address. SC -> 0.
• Micro-operations use common bus + control signals.

2. Decode Phase

• Control Unit decodes opcode in $IR(0-2)$ or $IR(12-14)$ depending on model, and indirect bit $I$.
• Decodes addressing mode, determines instruction type: Memory-reference (7 ops: AND, ADD, LDA, STA, BUN, BSA, ISZ), Register-reference, I/O.
• Generates control signals for next phase. No bus transfer, just combinational decode.
• $T_2: D_0...D_7 \leftarrow Decode(IR_{12-14}), AR \leftarrow IR_{0-11}, I \leftarrow IR_{15}$

3. Execute Phase

• Performs operation specific to opcode. Different $T_3, T_4...$ micro-ops.

Examples:

• LDA (Load AC): $T_4: DR \leftarrow M[AR]$, $T_5: AC \leftarrow DR, SC\leftarrow0$
• ADD: $T_4: DR \leftarrow M[AR]$, $T_5: AC \leftarrow AC+DR, E\leftarrow C_{out}, SC\leftarrow0$
• BUN (Branch Unconditional): $T_4: PC \leftarrow AR, SC\leftarrow0$
• Register-reference (e.g., CLA, CMA) executed at $T_3$ in one cycle.
• Indirect cycle adds AR <- M[AR] if $I=1$ ($T_3$).

After execute, $SC$ cleared to 0, cycle repeats for next instruction.

Diagram / Flow

+------+     Fetch      +------+    Decode     +--------+    Execute    +------+
|  PC  | ------------> |  IR  | ------------> | Control| ------------> |  ALU |
| AR   |  M[AR]->IR    |      |  opcode->D   |  Unit  |  micro-ops    |  AC  |
| MEM  |  PC++         |      |  AR<-addr    |        |  AC<-AC+DR    |  DR  |
+------+               +------+               +--------+  PC<-AR etc   +------+
   ^                                                                  |
   |<---------------------- SC=0, next instruction -------------------|

Timing: Each phase takes 1+ clock cycles; CPI = cycles per instruction (1 for simple, 5-6 for memory-reference). Interrupts checked after Execute before next Fetch: if R=1: handle interrupt (save PC -> M[0], PC=1).

Pipelined CPUs overlap F-D-E of successive instructions; single-cycle vs multi-cycle vs pipelined designs differ in how many clocks per phase.