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COMPUTER ORGANIZATION & ARCHITECTUREA non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz. (a) What is the speedup achieved for a typical program? (b) What is the MIPS rate for each processor?202214mOPERATING SYSTEMThe CPU utilization when the system is ______ (i) timesharing (ii) thrashing (iii) multiprocessing (iv) None of the above20232mCOMPUTER ORGANIZATION & ARCHITECTURELet a be the percentage of a program code that can be executed simultaneously by n processors in a computer system. Assume that the remaining code must be executed sequentially by a single processor. Each processor has an execution rate of x MIPS. (a) Derive an expression for the effective MIPS rate when using the system for exclusive execution of this program, in terms of n, \alpha, and x. (b) If n=16 and x=4 MIPS, determine the value of that will yield a system performance of 40 MIPS.202214mCOMPUTER ORGANIZATION & ARCHITECTUREHow do instruction set, compiler technology, CPU implementation and control, and cache and memory hierarchy affect the CPU performance? Justify the effects in terms of program length, clock rate and effective CPI.20197m