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COMPUTER ORGANIZATION & ARCHITECTURE### 3. A program runs on a 10 GHz CPU with the instruction mix and corresponding clock cycle count as given in the table: | Instruction type | Clock cycle count | Instruction count | | ---------------- | ----------------- | ----------------- | | Control transfer | 5 | 5000 | | Data transfer | 4 | 4000 | | Floating point | 2 | 2000 | | Integer | 1 | 1000 | --- ### Determine the following: - (a) CPI - (b) Execution time - \(c\) MIPS rate for program201414mCOMPUTER ORGANIZATION & ARCHITECTUREA non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz. (a) What is the speedup achieved for a typical program? (b) What is the MIPS rate for each processor?202214mOPERATING SYSTEMThe CPU utilization when the system is ______ (i) timesharing (ii) thrashing (iii) multiprocessing (iv) None of the above20232mComputer NetworksA pure ALOHA network transmits 200-bit frames on a shared channel of 200 kbps. What is the throughput, if the system (all stations together) produces (i) 1000 frames per second and (ii) 500 frames per second?20217m