Given: 16 registers → $4$ bits to address, 32 ALU ops → $5$ bits, 8 shifter ops → $3$ bits. Common bus system: any register can drive bus (SEL A, SEL B), any register can be destination.

(i) Control Word Format

For register-to-register micro-operation via two bus passes or one ALU+shifter path:

Field	Bits	Function
SELA	4	Select source register A to bus → ALU A input
SELB	4	Select source register B to bus → ALU B input
SELD	4	Select destination register to receive result
ALUF	5	ALU operation select
SHF	3	Shifter operation select
Total	20

Format: SELA (4) | SELB (4) | SELD (4) | ALUF (5) | SHF (3) = 20-bit control word. If including control bits for bus enable, memory, etc., additional bits may be added, but core is 20 bits.

Encoding: Registers: $R0=0000, R1=0001, R2=0010, R3=0011, R4=0100, R5=0101, R6=0110,\dots,R15=1111$.
ALU ops example: $ADD=00010$, $SUB=00011$, etc. Shifter: $No\_shift/Pass=000$, $SHL=001$, etc.

(ii) Bits for $R4 \leftarrow R5 + R6$

• SELA = $R5 = 0101$
• SELB = $R6 = 0110$
• SELD = $R4 = 0100$
• ALUF = $ADD = 00010$ (assuming code 00010 for ADD)
• SHF = $No\ shift = 000$

Control word = 0101 0110 0100 00010 000

In hex grouping: 0x5 6 4 02 0 → binary 01010110010000010000 = 0x56410 (20 bits).

If shifter field considered at LSB side, full 20-bit word: SELA SELB SELD ALUF SHF = 0101 0110 0100 00010 000.

Micro-operation execution: Bus: $R5 \rightarrow ALU.A$, $R6 \rightarrow ALU.B$, ALU performs $A+B$, result through shifter (unshifted) → bus → $R4$ latch via SELD decode.

If microinstruction also contains SEQ bits for next-address, additional bits for carry-in etc. would extend word, but core operation bits as above.