Types of Registers and Common Bus System

A. Types of Registers in Basic Computer (Mano Model - 8 registers)

Basic computer has 8 registers of different function and size:

Register	Size	Function
DR - Data Register	16-bit	Holds memory operand brought from memory
AR - Address Register	12-bit	Holds address for memory (since memory $4096 \times 16$)
AC - Accumulator	16-bit	Processor register, result of ALU operations, central for processing
IR - Instruction Register	16-bit	Holds instruction code after fetch (opcode 0-11 + address 12-bit)
PC - Program Counter	12-bit	Holds address of next instruction
TR - Temporary Register	16-bit	Temporary storage for ALU operand
INPR - Input Register	8-bit	Holds input character from input device
OUTR - Output Register	8-bit	Holds output character for output device
SC - Sequence Counter	4-bit	Provides sequence $T_0...T_{15}$ for control timing

Other classifications:

• General Purpose Registers (AX, BX, CX, DX in 8086) vs Special Purpose (PC, IR, MAR, MDR, SP, Flag)
• User-visible vs Internal (MAR, MBR/MDR)
• By function: Data, Address, Status/Flag (EFLAGS), Control (PC, IR, SC)

B. Basic Computer Registers Connected to Common Bus

To avoid $N \times N$ wiring, all registers are connected via a single common bus using multiplexers.

Scheme: 7 registers + memory unit each provide 16-bit (or 12-bit) outputs to an 8-to-1 multiplexer arrangement (actually 4× 16-bit 8:1 MUX or 16× 8:1). Selection lines $S_2 S_1 S_0$ select one source to place on bus.

Selection S2 S1 S0 | Register selected on Bus
---------------------|------------------------
  000                | DR  (16-bit)
  001                | AR  is 12-bit (padded)
  010                | AC
  011                | IR
  100                | PC  (12-bit)
  101                | TR
  110                | Memory (M[AR] -> 16-bit)
  111                | (un-used)

         +----+  +----+  +----+  +----+  +----+  +----+  +--------+
 DR(16)--|    |  |    |  |    |  |    |  |    |  |    |  |        |
 AR(12)--|    |  |    |  |    |  |    |  |    |  |    |  |  4 x   |
 AC(16)--| 16x8:1 MUX for bit0 | ... | MUX for bit15  |---- COMMON BUS (16 lines) ----> to inputs of all registers (LD input)
 IR(16)--|    |  |    |  |    |  |    |  |    |  |    |  |        |
 PC(12)--|    |  |    |  |    |  |    |  |    |  |    |  |        |
 TR(16)--|    |  |    |  |    |  |    |  |    |  |    |  |        |
 MEM(16)--|    |  |    |  |    |  |    |  |    |  |    |  |        |
         +----+  +----+  +----+  +----+  +----+  +----+  +--------+
                ^ S2 S1 S0 from Control Unit

• Bus is only one source at a time: Control unit asserts $S_2 S_1 S_0$ to select source.
• Destination register has LD (Load) control signal: e.g., AR <- Bus when $LD_{AR}=1$ at clock edge.
• Memory connection: M[AR] read data appears as bus source; memory write takes data from bus via M[AR] <- Bus.
• 12-bit registers (AR, PC) connected to lower 12 lines, upper 4 lines tied to 0.

Control examples:

• $T_0: AR \leftarrow PC$ => $S_2S_1S_0=100$, $LD_{AR}=1$
• $T_1: IR \leftarrow M[AR], PC \leftarrow PC+1$ => $S=110$, $LD_{IR}=1$
• $T_4: DR \leftarrow M[AR]$ => $S=110$, $LD_{DR}=1$

Advantage: One bus reduces wires from $O(n^2)$ to $O(n)$, multiplexer selection is simple combinational logic.