Registers of a Non-Pipelined (Single-Cycle / Multi-cycle) CPU

In a non-pipelined CPU only one instruction is in execution at a time (fetch-decode-execute completes before next fetch). Registers are small, fast storage inside CPU.

1. Main Register Set

Register	Full Name	Size (typ)	Purpose
PC	Program Counter	16/32/64-bit	Holds address of next instruction to fetch. Incremented after fetch; loaded with branch target on jump.
IR	Instruction Register	16-32 bit	Holds current instruction opcode + operand fields after fetch. Decoded to generate control signals.
MAR	Memory Address Register	same as address bus	Buffers address to be sent to memory. MAR ← PC for fetch, MAR ← operand address for data.
MBR/MDR	Memory Buffer/Data Register	word size	Buffers data to/from memory. MBR ← M[MAR] on read; M[MAR] ← MBR on write. Isolates CPU from memory bus timing.
AC	Accumulator	word size	Implicit operand and result register in accumulator machines. ALU operations: AC ← AC op MBR. Single AC minimizes address field.
GPRs R0-Rn	General Purpose Registers	word size	Hold operands, addresses, intermediate results, loop counters. Reduce memory accesses.
SP	Stack Pointer	address size	Points to Top-Of-Stack for PUSH/POP, CALL/RET. SP ← SP ±1 automatically.
PSW/FLAGS	Processor Status Word / Condition Codes	8-32 bit	Flags: Z(Zero), C(Carry), N(Negative/Sign), V(Overflow), P(Parity), I(Interrupt enable). Set by ALU, tested by branches.
Index / Base Registers	X, BR	address size	Effective address calculation: EA = BR + Index + displacement for arrays.
Temporary / Buffer Registers	TMP, Y, Z	word size	Invisible to programmer, hold intermediate ALU inputs (e.g., TMP ← R1 ; R3 ← TMP + R2). Needed because ALU is combinational.

Some CPUs also have: SC (Sequence Counter), AR, DR in textbook (Mano) notation.

2. Diagram - Datapath with Registers (Non-Pipelined)

        +----+    +----+    +------+
 PC --->| MAR|-->|Memory|--->| MBR  |----> IR (opcode)
        +----+    +----+    +------+       |
           ^                  |            v
           |                  v        Control Unit
           +--------------->+-----+       |
                          | ALU |<--AC/GPRs--> Registers
                          +-----+       |
                             |      PSW/FLAGS
                             v
                           MDR/MAR path to memory

3. Operation Flow (Example: ADD M[X])

1. MAR ← PC ; PC ← PC+1
2. MBR ← M[MAR] ; IR ← MBR (Fetch)
3. Decode IR
4. MAR ← IR(address) ; MBR ← M[MAR]
5. AC ← AC + MBR ; Z,C,N,V updated in PSW

All registers hold values stable for the whole cycle; non-pipelined means no overlapping - next instruction waits until write-back finishes, so no pipeline registers needed, but CPI = 1 (single-cycle, long clock) or CPI >1 (multi-cycle).