Differentiate between Expansion and Extension of Memory

Although both are techniques to increase memory capacity using smaller chips, they address different dimensions: depth (words) vs. width (bits). Sometimes textbooks use the terms interchangeably, but standard distinction is:

Aspect	Memory Expansion (Word/Depth Expansion)	Memory Extension (Bit/Width Extension)
Goal	Increase number of words (depth) e.g., $1K\times8$ -> $4K\times8$	Increase word length / bits per word (width) e.g., $1K\times4$ -> $1K\times8$
What is increased	Address space (more addresses)	Data bus width (more bits per address)
Address lines	Extra MSB lines needed for chip selection; address split into chip-select + intra-chip address	Same address lines to all chips; no extra address decoding for width
Data lines	Data width unchanged; chips' data buses share via tri-state/bus, only one active at a time	Data buses concatenated; each chip contributes part of word, all active simultaneously
Chip Select (CS) logic	Decoder required: $m$-to-$2^{m}$ decoder driven by high-order address bits enables one chip at a time	No decoder: CS of all chips tied together (common CS), all chips enabled together
Connection	Address buses common, data buses common (wired-OR via tri-state), CS decoded	Address buses common, data buses split/combined, CS common
Example	Four $1K\times8$ to make $4K\times8$: <br> A0-A9 to all chips, A10-A11 -> 2:4 decoder -> CS0-CS3. Data D0-D7 common bus.	Two $1K\times4$ to make $1K\times8$: <br> A0-A9 to both, CS0=CS1= CS, Chip1 D0-D3 -> system D0-D3, Chip2 D0-D3 -> system D4-D7.
Diagram	CPU A0-A9 ----> all chips A0-A9<br>`CPU A10-A11 -> Decoder -> CS0	CS1
Analogy	Adding more pages to a book (more pages)	Widening each page (more columns per page)

Diagrams

Expansion (Depth) $2K\times8$ using $1K\times8$ x2:

          A0-A9 +----------------+
      +---------->| 1Kx8 Chip0   |----> D0-D7 --+
      |           +----------------+            | Tri-state
A0-A9-+           +----------------+            +--> System D0-D7
      +---------->| 1Kx8 Chip1   |----> D0-D7 --+
      |           +----------------+
A10 --> Decoder -> CS0 (A10=0), CS1 (A10=1)  (only one active)

Extension (Width) $1K\times8$ using $1K\times4$ x2:

A0-A9 ------> +--------+  D0-D3 ----> System D0-D3
              |1Kx4 C0 |
CS   -------->|        |
              +--------+
A0-A9 ------> +--------+  D0-D3 ----> System D4-D7
              |1Kx4 C1 |
CS   -------->|        |
              +--------+

Combined: To make $4K\times16$ from $1K\times8$ chips, do both: need 4 groups (expansion) each with 2 chips in parallel (extension) = 8 chips.

In short: Expansion = more words, Extension = wider words. Both together give arbitrary $M \times N$ memory from $m \times n$ chips.