Solution - RAM Chip Organization & SRAM vs DRAM

A) Organization of a Typical RAM Chip:

A RAM chip of size $2^k \times m$ (e.g., $1024 \times 8$, $16K \times 1$) has:

• Memory Array: Matrix of memory cells arranged in rows $\times$ columns. For $1024 \times 8$, 8192 cells (128 rows $\times$ 64 columns).
• Address Decoder: $k$ address lines decoded to select one row/word. Row decoder selects row, column decoder selects bit group. Example: 10 lines for 1024 words (5 for row, 5 for column or 10 for row).
• Memory Cells: Each cell stores 1 bit (flip-flop for SRAM, capacitor+transistor for DRAM).
• Chip Select (CS) / Chip Enable (CE): Enables chip only when selected - allows building larger memories by combining chips.
• Read/Write Control (RD/WR, WE, OE): $W=0$ write enabled, $W=1$ read.
• Bidirectional Data Lines ($I/O_{0}..I/O_{m-1}$): Input data for write, output for read - tri-state buffers. $m$ lines = word length.
• Address Lines ($A_0..A_{k-1}$): Input address.

Construction of larger memory: Using chip select and address decoding. Eg., to make $2K \times 8$ from two $1K \times 8$ chips, $A_{10}$ drives CS via decoder.

Block diagram: Address Lines -> Row/Column Decoder -> Memory Cell Array -> Sense Amplifiers / Write Drivers -> Data Lines. Control logic coordinates CS, OE, WE.

B) Difference between Static RAM (SRAM) and Dynamic RAM (DRAM):

Parameter	Static RAM (SRAM)	Dynamic RAM (DRAM)
Cell Design	6 transistors (bistable latch/flip-flop)	1 transistor + 1 capacitor (charge storage)
Storage	Holds data as long as power on (static)	Charge leaks, needs periodic refresh every ~2ms
Refresh Circuit	Not needed	Required (refresh controller, ROW strobing)
Density	Low (6T per bit)	High (1T per bit) - 4-5x denser
Speed	Fast (access 1-10 ns, no refresh overhead)	Slower (access 50-70 ns + refresh)
Power	More power per cell, but no refresh power	Less per cell, but refresh consumes power
Cost	Costly per bit	Cheap per bit
Use	Cache (L1,L2,L3), fast buffers, registers	Main memory (DDR SDRAM)
Volatility	Volatile (like DRAM)	Volatile

Summary: SRAM = speed, DRAM = density & cost-effectiveness for large memory.

Typical RAM Chip Pin Diagram: $A_0-A_9$, $D_0-D_7$, $\overline{CS}$, $\overline{WE}$, $\overline{OE}$, $V_{cc}$, $GND$.