Organization of SRAM and DRAM [7M]

Semiconductor main memory built from MOS cells.

1. SRAM Cell (Static RAM):

• Cell: 6-transistor (6T) flip-flop - 4 transistors form cross-coupled inverters (latch) + 2 access transistors, or 4T + 2 resistors. Stores bit as long as power on - no refresh.
• Operation: Word line (WL) enables access transistor, bit lines $B$ and $\bar{B}$ read/write differentially. Sense amplifier detects small swing.
• Organization: Array of $m \times n$ cells with row decoder, column decoder/mux, sense amps. Example 1Kx8 chip: 32x32 array, 5-bit row decode, 5-bit column.
• Characteristics: Access time 1-10 ns (cache speed), density low (6T area large), cost high, power moderate (static + dynamic). No refresh logic.

2. DRAM Cell (Dynamic RAM):

• Cell: 1 Transistor + 1 Capacitor (1T1C). Capacitor stores charge (charged=1, discharged=0). Transistor acts as switch to bitline.
• Destructive read: Reading discharges capacitor onto bitline; data must be written back (restore) via sense amp (which also acts as latch). Charge leaks within ms -> refresh needed.
• Organization: Folded bitline architecture; rows called pages. Access: RAS (row address) latches row into row buffer (sense amps), CAS selects column. Burst mode.
• Refresh: Each row must be refreshed every $t_{REF}$ typically 64ms. Refresh is RAS-only cycle reading row and restoring. Controller does distributed refresh: e.g. 8192 rows /64ms => one row every $7.8\mu s$ . Overhead ~1-2% bandwidth. Variations: Burst, distributed, hidden refresh.
• Characteristics: Access time 40-70 ns, cycle time longer due to precharge, but density high (1T vs 6T), cost per bit 1/8th of SRAM, low power per bit, needs refresh + precharge overhead.

3. Chip Organization Example:

Build larger memory from chips: $n$ chips in parallel for word width, address decoding across chips. e.g. To make $16K \times 8$ from $4K \times8$ chips, need 4 chips, 2-bit chip-select decode from $A_{12},A_{13}$.

Internal: $2^k$ words, $w$ bits: decoder $k \to 2^k$, array $2^k \times w$.

Modern DDR SDRAM: Banks (4-16) -> each bank is DRAM array with row buffer; interleaving across banks hides precharge. Synchronous burst: access time defined as $CL$ (CAS latency).

4. Comparison:

Feature	SRAM	DRAM
Cell	6T latch	1T1C capacitor
Density	Low	High (4-8x)
Access	1-10 ns, no refresh	50 ns + refresh, slower
Refresh	No	Yes ~64ms
Cost/bit	High	Low
Use	Cache (L1/L2/L3), register file	Main memory (DIMMs), frame buffer
Power	High leakage	Low per bit, refresh power

System: SRAM for cache where speed matters, DRAM for main memory where capacity/cost matters. Emerging: SRAM+DRAM+3D stacked (HBM).