2014 question paper
COMPUTER ORGANIZATION & ARCHITECTURE
23 questions
Q1a. Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the effective address of the memory operand in each of the following instructions? - (i) Load 20(R1), R5 - (ii) Add –(R2), R520142m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the effective address of the memory operand in each of the following instructions?
- (i) Load 20(R1), R5
- (ii) Add –(R2), R5
Q1b. What is the use of condition code register?20142m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What is the use of condition code register?
Q1b. Explain MIPS and MFLOPS.20147m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain MIPS and MFLOPS.
Q1c. **What do you mean by end-around carry correction?20142m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →**What do you mean by end-around carry correction?
Q1d. Discuss the role of Booth algorithm in the design of fast multipliers.20142m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Discuss the role of Booth algorithm in the design of fast multipliers.
Q1e. Why is the wait-for-memory-function-completed step needed when reading from or writing to the main memory?20142m
Module 4: Memory Organization
View this question on its own page →Why is the wait-for-memory-function-completed step needed when reading from or writing to the main memory?
Q1f. Write the sequence of control steps required for three-bus structure for the following instruction: - Add R4, R5, R620142m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Write the sequence of control steps required for three-bus structure for the following instruction:
- Add R4, R5, R6
Q1g. Define locality of reference.20142m
Q1h. Give the features of a ROM cell.20142m
Q1i. What is the difference between a subroutine and an interrupt service routine?20142m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What is the difference between a subroutine and an interrupt service routine?
Q1i. Define bus arbitration.20142m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Define bus arbitration.
Q2a. Explain Flynn’s classification of computer system architecture.20147m
Module 3: Pipelining
View this question on its own page →Explain Flynn’s classification of computer system architecture.
Q3. ### 3. A program runs on a 10 GHz CPU with the instruction mix and corresponding clock cycle count as given in the table: | Instruction type | Clock cycle count | Instruction count | | ---------------- | ----------------- | ----------------- | | Control transfer | 5 | 5000 | | Data transfer | 4 | 4000 | | Floating point | 2 | 2000 | | Integer | 1 | 1000 | --- ### Determine the following: - (a) CPI - (b) Execution time - \(c\) MIPS rate for program201414m
Module 3: Pipelining
View this question on its own page →3. A program runs on a 10 GHz CPU with the instruction mix and corresponding clock cycle count as given in the table:
Instruction type Clock cycle count Instruction count Control transfer 5 5000 Data transfer 4 4000 Floating point 2 2000 Integer 1 1000
Determine the following:
- (a) CPI
- (b) Execution time
- (c) MIPS rate for program
Q4a. Explain fetch-decode-execution cycle.20147m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain fetch-decode-execution cycle.
Q4b. Differentiate between hardwired programmed control and microprogrammed control.20147m
Module 4: Memory Organization
View this question on its own page →Differentiate between hardwired programmed control and microprogrammed control.
Q5a. Explain stack-based architecture of a CPU with the help of a diagram.20147m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain stack-based architecture of a CPU with the help of a diagram.
Q5b. List registers of a non-pipelined CPU. Explain the purpose of each register.20147m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →List registers of a non-pipelined CPU. Explain the purpose of each register.
Q6(a). Differentiate between expansion and extension of memory.20147m
Module 4: Memory Organization
View this question on its own page →Differentiate between expansion and extension of memory.
Q6b. Describe organization of a typical RAM chip. Differentiate between static RAM chip and dynamic RAM chip.20147m
Module 4: Memory Organization
View this question on its own page →Describe organization of a typical RAM chip. Differentiate between static RAM chip and dynamic RAM chip.
Q7a. Explain swapping. Why is it used in memory management?20147m
Module 4: Memory Organization
View this question on its own page →Explain swapping. Why is it used in memory management?
Q7b. Explain virtual memory. Explain the role of logical as well as physical address.20147m
Module 4: Memory Organization
View this question on its own page →Explain virtual memory. Explain the role of logical as well as physical address.
Q8. Explain the use of DMA controllers in a computer system with a neat diagram.201414m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain the use of DMA controllers in a computer system with a neat diagram.
Q9. Explain handshake protocol. Depict clearly how it controls data transfer during an input operation.201414m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain handshake protocol. Depict clearly how it controls data transfer during an input operation.