2014 question paper

COMPUTER ORGANIZATION & ARCHITECTURE

23 questions

1. Q1a. Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the effective address of the memory operand in each of the following instructions? - (i) Load 20(R1), R5 - (ii) Add –(R2), R520142m

   Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

   Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the effective address of the memory operand in each of the following instructions?

   • (i) Load 20(R1), R5
   • (ii) Add –(R2), R5

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   Worked Solution

   Answer: Effective Address calculation:

   Given R1=1200, R2=4600
   (i) Load 20(R1), R5 → Indexed/Displacement mode: EA = R1 + 20 = 1200+20 = 1220. Content at memory 1220 loaded into R5.
   (ii) Add -(R2), R5 → Autodecrement mode: First R2 = R2 - word size (assume 4 for 32-bit or 1 for simplicity; textbook uses R2 = 4600-1 = 4599 if byte, or 4596 if word). If byte-addressable decrement by 2? Typically -(R) means R ← R - size, then EA = R (new). So EA = 4599 (byte) or 4596 (word), value at that address added to R5. If size unspecified, EA = R2 -1 = 4599.

2. Q1b. Explain MIPS and MFLOPS.20147m

   Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

   Explain MIPS and MFLOPS.

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   Worked Solution

   MIPS and MFLOPS - Performance Measures

   1. MIPS - Million Instructions Per Second:
   $$MIPS = \frac{\text{Instruction Count}}{Execution\ Time \times 10^6} = \frac{f_{clock}}{CPI \times 10^6}$$
   where $f_{clock}$= clock frequency, $CPI$= cycles per instruction.

   Measures integer/overall CPU throughput. e.g., CPU @ 2 GHz with CPI=2: $MIPS = 2000/(2)=1000$ MIPS.

   Limitations of MIPS:

   • Depends on instruction set - one ISA's instruction does more work than another.
   • Ignores instruction complexity and mix.
   • Not reliable for comparing different architectures or compilers.

   2. MFLOPS - Million Floating Point Operations Per Second:
   $$MFLOPS = \frac{\text{No. of Floating Point Operations}}{Execution\ Time \times 10^6}$$
   Measures capability for scientific/numerical workload (add, mul, div on floats). Higher MFLOPS = better for supercomputing.

   Limitations: Only counts FP ops, ignores integer, branch, I/O; depends on program (Linpack, etc) and compiler optimization.

   Comparison: MIPS $\approx$ general-purpose speed, MFLOPS $\approx$ scientific speed. MFLOPS rating typically lower than MIPS on same machine because FP ops take more cycles. Both are crude; today SPEC, CPI, execution time preferred.

3. Q1b. What is the use of condition code register?20142m

   Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

   What is the use of condition code register?

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   Condition Code Register (CCR) / Flag Register Uses:

   CCR holds flags N, Z, V, C set by ALU after arithmetic/logic operation:

   • N (Negative): N=1 if result MSB=1 (negative in 2's complement). Used for signed branch (BMI/BPL).
   • Z (Zero): Z=1 if result = 0. Used to test equality (BEQ/BNE) and loop termination.
   • V (Overflow): V=1 if signed 2's complement overflow (result exceeds range). Used for signed arithmetic error detection.
   • C (Carry): C=1 if carry out from MSB (unsigned overflow) or borrow. Used for multi-precision addition/subtraction (ADC/SBC), unsigned comparison (BCS/BCC).

   Uses: Conditional branching, decision making (CMP + flags), interrupt control, and detecting arithmetic errors without extra comparator.

4. Q1c. **What do you mean by end-around carry correction?20142m

   Module 1: Functional Block of computer and Data representaion

   **What do you mean by end-around carry correction?

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   Worked Solution

   End-Around Carry (EAC) Correction - 1's Complement Addition:

   In 1's complement, negative numbers are bitwise complements. When adding, a carry out of MSB is not discarded but added back to LSB (end-around carry).

   Rule: Add numbers as unsigned. If carry-out $C_{out}=1$, add 1 to result to get correct sum.

   Example: Add $+5$ (0101) and $-3$ (1100 in 1's complement):
   0101 + 1100 = 10001 -> 4-bit result 0001 with $C_{out}=1$. Add EAC: 0001+1 = 0010 (2), which is correct ($5-3=2$).

   If no carry ($C_{out}=0$), result is already correct and negative (1's complement) if MSB=1. Double complement case $1111$ represents -0.

5. Q1d. Discuss the role of Booth algorithm in the design of fast multipliers.20142m

   Module 1: Functional Block of computer and Data representaion

   Discuss the role of Booth algorithm in the design of fast multipliers.

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   Worked Solution

   Booth Algorithm — Role in Fast Multipliers (2m):

   Booth's algorithm enables fast signed (two's complement) multiplication with fewer add/sub operations.

   • Standard shift-and-add requires an addition for every 1 in multiplier. Booth recodes multiplier and examines pairs of bits ($Q_0, Q_{-1}$):
     • 00 or 11 → arithmetic right shift only
     • 01 → Add multiplicand (A = A + M)
     • 10 → Subtract multiplicand (A = A - M)
       followed by arithmetic right shift.
   • Handles positive and negative operands uniformly without separate sign correction.
   • Reduces number of operations for strings of 1s (e.g., 01110 handled with one add and one subtract), speeds up multiplier and naturally supports efficient hardware (Booth recoding, Modified Booth Radix-4).
   • Basis for modern high-speed array / Wallace-tree multipliers.
6. Q1e. Why is the wait-for-memory-function-completed step needed when reading from or writing to the main memory?20142m

   Module 4: Memory Organization

   Why is the wait-for-memory-function-completed step needed when reading from or writing to the main memory?

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   Worked Solution

   Why WMFC is needed:

   Main memory (DRAM) is asynchronous and slower than CPU. Its access time is variable and longer than one CPU clock period. CPU issues read/write by placing address/data on bus and issues Memory Enable but cannot proceed until memory completes the operation.

   WMFC (Wait-for-Memory-Function-Completed) is a control step where CPU waits for MFC (Memory Function Completed) signal from memory controller.

   • Ensures data in MDR/MBR is valid before it is used (read) or guarantees write has been latched.
   • Synchronizes fast synchronous CPU with slow asynchronous memory.
   • Without WMFC, CPU would fetch stale/wrong data or overwrite next operation, causing incorrect execution. Cycle time = access time + recovery time, so next memory operation can start only after WMFC/MFC.

   In synchronous control sequence: MAR ← address; MDR ← data (for write); WMFC; MDR ← valid data (for read).

7. Q1f. Write the sequence of control steps required for three-bus structure for the following instruction: - Add R4, R5, R620142m

   Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

   Write the sequence of control steps required for three-bus structure for the following instruction:

   • Add R4, R5, R6

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   Worked Solution

   Three-bus Structure – Add R4, R5, R6 (meaning $R4 \leftarrow R5 + R6$)

   In three-bus organization, bus A and bus B supply operands and bus C carries result, so execution needs only one clock cycle (fetch/decode steps same as usual).

   Sequence:

   1. Fetch & Decode: PC_{out}, MAR_{in}, Read, WMFC; MDR_{out}, IR_{in}; PC_{inc}; Decode
   2. Execute Add: R5_{outA}, R6_{outB}, ALU_{add}, R4_{inC}, End

   Explanation: Contents of R5 placed on Bus A, R6 on Bus B, ALU adds them concurrently, result on Bus C is latched into R4.

   Note: For single-bus it would need 3 steps: R5_{out}, Y_{in}; R6_{out}, Y+ R6 → Z; Z_{out}, R4_{in}. For two-bus: R5_{outA}, R6_{outB}, ALU → Z; Z_{out}, R4_{in}. Three-bus is fastest.

8. Q1g. Define locality of reference.20142m

   Module 4: Memory Organization

   Define locality of reference.

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   Locality of Reference - Defined (2 Marks)

   Locality of reference is the empirical observation that memory references tend to cluster in a small region over a short time interval. It is the basis for cache and virtual memory.

   1. Temporal Locality: If a memory location is referenced, it is likely to be referenced again soon. e.g. loops, reusable variables, stack. Keeping recently used blocks in cache yields hits.

   2. Spatial Locality: If a location is referenced, nearby locations are likely to be referenced soon. e.g. sequential instruction fetch, arrays. Fetching a whole block/line exploits this.

   3. Sequential Locality: Special case of spatial — ordered instruction execution.

   Due to locality, 90/10 rule holds: 90% of time CPU accesses only 10% of address space, making cache hierarchy very effective.

9. Q1h. Give the features of a ROM cell.20142m

   Module 4: Memory Organization

   Give the features of a ROM cell.

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   ROM Cell Features (2 Marks)

   ROM (Read Only Memory) cell stores a fixed bit permanently:

   1. Non-volatile: Retains contents without power — used for bootstrap, firmware, microprogram.

   2. Mask-programmed: Contents written at fabrication via contact mask / transistor presence (1 = transistor present, 0 = absent). Not field-writable.

   3. Non-destructive read: Reading does not erase cell; access via address decoder → word line → bit line sense.

   4. High density, low cost/bit for large volumes; slower write-once but fast read comparable to RAM.

   5. Variants: PROM (fusible link, OTP), EPROM (floating gate, UV erase), EEPROM/Flash (electrically erasable) retain ROM cell principle but allow reprogramming.

   Single ROM cell = 1 transistor + contact/via; array is OR plane of word lines.

10. Q1i. Define bus arbitration.20142m

    Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

    Define bus arbitration.

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    Worked Solution

    Answer: Bus Arbitration - Definition

    Bus Arbitration is the process of resolving contention when multiple bus masters (CPU, DMA controller, processors in multiprocessor system, I/O controllers) simultaneously request control of the system bus. Since only one master can drive the bus at a time, an arbiter decides priority and grants bus access.

    Need: Prevents collision and ensures orderly transfer.

    Approaches:

    1. Centralized Arbitration: Single hardware arbiter (e.g., priority encoder) grants bus via Bus Request ($BR$) / Bus Grant ($BG$) daisy-chain or independent requests.
    2. Distributed Arbitration: Each master has its own arbitration logic and decides collectively (e.g., self-selection).

    Common schemes: Daisy chaining, Polling, Independent Request (Parallel arbitration). Priority may be fixed, rotating, or dynamic.

    In short, bus arbitration = mechanism to select one master among contenders to become next bus master.

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12. Q1i. What is the difference between a subroutine and an interrupt service routine?20142m

    Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

    What is the difference between a subroutine and an interrupt service routine?

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    Worked Solution

    Subroutine vs Interrupt Service Routine (ISR):

    Feature	Subroutine (Procedure)	Interrupt Service Routine (ISR / Interrupt Handler)
    Invocation	Synchronous, explicitly called by program via CALL instruction	Asynchronous, invoked by hardware signal (INTR, NMI) or exception/trap. CPU diverts without program request
    Control	Program has control - known location in code flow	Unpredictable timing, depends on external event / fault
    Linkage	CALL saves return address (PC) on stack; RET returns	Interrupt logic saves PC and PSW/FLAGS automatically; return via IRET/RETI
    Context Saving	Caller may save few registers (convention dependent)	Must save entire processor state (registers, flags) as interrupt can occur between any two instructions
    Priority/Nesting	No priority concept, normal nesting via calls	Has priority; higher priority interrupts can preempt lower ISR; requires PIC (8259) arbitration
    Synchronization	Blocking / sequential flow	Must be reentrant, short, ends with EOI to PIC; often disables interrupts at entry

    Key Idea: Subroutine = software-initiated planned transfer; ISR = hardware-initiated event-driven transfer that transparently suspends current task. Example: CALL SORT vs keyboard ISR at vector 21h invoked on key press.

13. Q2a. Explain Flynn’s classification of computer system architecture.20147m

    Module 3: Pipelining

    Explain Flynn’s classification of computer system architecture.

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    Worked Solution

    Flynn's Classification of Computer Architecture (7M)

    Proposed by Michael J. Flynn (1966) - classifies parallel architectures based on number of Instruction streams vs Data streams.

    Streams = independent sequence of instructions / data as seen by CPU.

                        Single Data (SD)
                        One data stream
                       ┌─────────────────
                       │
    Single Instruction │   SISD
    Single instruction │
    stream             │   (von Neumann)
                       │
    -------------------+---------------------------------
                       │
    Multiple Instruction│  MISD
    Multiple instruction│ (rare - systolic)
    stream             │
                       └─────────────────
                        Multiple Data (MD)
                        Multiple data streams
    Actually 2x2 grid:
             ┌─────────────┬──────────────┐
             │  SD         │  MD          │
    ─────────┼─────────────┼──────────────┤
     SI      │  SISD       │  SIMD        │
    ─────────┼─────────────┼──────────────┤
     MI      │  MISD       │  MIMD        │
             └─────────────┴──────────────┘
    

    1. SISD - Single Instruction Single Data

    One instruction stream, one data stream. Sequential.

    • Architecture: Conventional Von Neumann uniprocessor. One CU fetches one instruction, one ALU operates on one data element at a time. (No parallelism)
    • Execution: IF -> ID -> EX -> MEM -> WB single thread.
    • Example: Intel 8086, 80386 uniprocessor, ARM single-core, IBM 360. Old mainframes.
    • Diagram:

      ┌────┐      ┌─────┐      ┌─────┐      ┌─────┐
      │ CU |----->| PU  |----->| MU  |  IS  DS -> Single pipeline
      └────┘      └─────┘      └─────┘
       (IS= Instruction Stream, DS=Data Stream, PU=Processing Unit, MU=Memory)
    

    • Performance: Limited by clock, CPI, pipelining is still SISD (ILP but not classified separately by Flynn). Speedup via pipelining/superscalar still logically SISD.

    2. SIMD - Single Instruction Multiple Data

    One instruction executed on multiple data elements in parallel (Lockstep). Data parallelism.

    • Architecture: One CU broadcasts same instruction to multiple Processing Elements (PEs)/ALUs, each with own data. Requires array of processors + interconnection network (shared memory or mesh).
    • Execution: Fetch once, decode once, execute simultaneously on N data:
      for (i=0..N-1) C[i] = A[i] + B[i] single instruction ADD does all.
    • Examples:
      • Vector processors: Cray-1, CDC STAR-100, TI ASC
      • Array processors: ILLIAC-IV (64 PEs), CM-2, DAP
      • Modern: GPU warp (SIMT - extension), Intel SSE/AVX (single core SIMD within register), AVX-512 executes 16 floats per instruction, Multimedia extensions MMX.
    • Diagram:

              ┌────┐
              │ CU |---- IS (same instruction broadcast) ----+
              └────┘                                         |
          ┌──────┼──────┬───────┐
          v      v      v       v
        ┌────┐┌────┐┌────┐  ┌────┐
        │PE0 ││PE1 ││PE2 │..│PEN │ each PE has own data DS0..DSN
        │ALU ││ALU ││ALU │  │ALU │
        └────┘└────┘└────┘  └────┘
          ↕     ↕     ↕       ↕  Data Memory Module 0..N or interleaved
    

    • Use: Matrix operations, image processing, graphics, scientific loops where same operation applied to large dataset. Excellent speedup for vectorizable code; branch divergence hurts (masking).
    • Types: Word-slice vs bit-slice, true array vs vector/pipelined.

    3. MISD - Multiple Instruction Single Data

    Multiple instruction streams on same single data stream. Rare/ theoretical.

    • Architecture: Multiple CUs each with distinct instruction on same data item, pipelined through stages. Data flows through chain of processors.
    • Example / Interpretation:
      • Pipeline / Systolic array where data flows X -> PE1 (Op1) -> PE2 (Op2) -> PE3 (Op3) each stage different instruction but same datum stream - e.g., real-time signal processing, fault-tolerant systems with redundant execution for voting (N-version).
      • Carnegie Mellon C.mmp (conceived but no commercial)
      • Some view pipeline within single CPU as MISD-like (IF,ID,EX operate on same instruction stream overlapped) but not true.
    • Diagram:

     DS ---->┌────┐    ┌────┐    ┌────┐
             │PE0 │--->│PE1 │--->│PE2 │----> Result
     IS0---->|CU0 | IS1|CU1 | IS2|CU2 |
    

    • Use: Almost no general-purpose machine purely MISD; considered for specialized: multiple frequency filters on same sample stream, cryptographic pipelines.

    4. MIMD - Multiple Instruction Multiple Data

    Multiple instruction streams, multiple data streams. True parallelism - autonomous processors.

    • Architecture: Multiple independent processors (each with own CU+ALU+Memory/Local) work on own instruction & data. Two flavors:
      • Shared Memory (Tightly coupled): SMP (Symmetric Multiprocessors) - bus/cache coherent shared address space. E.g., Multicore CPU (Intel i7 8 cores), Xeon server.
      • Distributed Memory (Loosely coupled): Message-passing - cluster, network of workstations (NOW), supercomputer. E.g., Beowulf cluster, IBM BlueGene, NUMA.
    • Execution: MIMD can execute completely independent tasks (MIMD - multiple Programs) or cooperate on single problem (parallel programs) via synchronization (lock, barrier, MPI_Send).
    • Examples: Multicore processors, Multiprocessors, Clusters, Grids, Multi-computer (Cray T3D, Intel Paragon).
    • Diagram:

      ┌────┐  ┌────┐          ┌────┐  ┌────┐
      │CU0 │->│PE0 │->DS0     │CU1 │->│PE1 │->DS1
      └────┘  └────┘          └────┘  └────┘
         IS0     \ shared/ \     IS1
                  Distribution Network (Bus/Crossbar/Network)
      ┌────┐  ┌────┐          ┌────┐  ┌────┐
      │CUN │->│PEN │->DSN  etc.
      └────┘  └────┘
    

    • Use: General-purpose parallel computing - database servers, OS multitasking, HPC. Most flexible; speedup limited by Amdahl's law: Speedup = 1 / (f + (1-f)/N).

    Comparison Table

    Class	Instr Streams	Data Streams	Parallelism	Examples	Use Case
    SISD	1	1	None (sequential)	8086, ARM single	Basic PC
    SIMD	1	N	Data parallel	ILLIAC, GPU warp, AVX	Vector/matrix
    MISD	N	1	Pipeline on data	Systolic (rare)	Fault tolerance, pipeline
    MIMD	N	N	Task parallel	Multicore, Cluster	General parallel

    Extended Classifications (Johnson, later): SISD vs pipelines etc., but Flynn remains standard.

    For exam: Draw 4 quadrants diagram + small block for each type with CU/PE and arrows.

14. Q3. ### 3. A program runs on a 10 GHz CPU with the instruction mix and corresponding clock cycle count as given in the table: | Instruction type | Clock cycle count | Instruction count | | ---------------- | ----------------- | ----------------- | | Control transfer | 5 | 5000 | | Data transfer | 4 | 4000 | | Floating point | 2 | 2000 | | Integer | 1 | 1000 | --- ### Determine the following: - (a) CPI - (b) Execution time - \(c\) MIPS rate for program201414m

    Module 3: Pipelining

    3. A program runs on a 10 GHz CPU with the instruction mix and corresponding clock cycle count as given in the table:

    Instruction type	Clock cycle count	Instruction count
    Control transfer	5	5000
    Data transfer	4	4000
    Floating point	2	2000
    Integer	1	1000

    ---

    Determine the following:

    • (a) CPI
    • (b) Execution time
    • (c) MIPS rate for program

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    Worked Solution

    Given Data

    Clock $f = 10$ GHz $\Rightarrow T_c = 1/f = 0.1$ ns $= 10^{-10}$ s

    Type	CPI$_i$ ($c_i$)	$I_i$
    Control	5	5000
    Data transfer	4	4000
    Floating	2	2000
    Integer	1	1000

    Total instructions $I = \sum I_i = 5000+4000+2000+1000 = 12000$

    Total cycles $C = \sum c_i I_i$

    $C = 5000\times5 + 4000\times4 + 2000\times2 + 1000\times1$
    $C = 25000 + 16000 + 4000 + 1000 = 46000$ cycles

    (a) CPI (Average Clock Cycles per Instruction)

    $CPI = \dfrac{C}{I} = \dfrac{46000}{12000} = 3.833... \approx 3.83$ cycles/instr

    If weighted: $CPI = \sum (I_i/I)\times c_i = 0.4167\times5 + 0.3333\times4 +0.1667\times2+0.0833\times1 =3.83$

    (b) Execution Time

    $T_{cpu}= C \times T_c = \dfrac{C}{f}$

    $T_{cpu}= \dfrac{46000}{10\times10^9}= 4.6\times10^{-6}$ s $= 4.6 \mu s$

    Alternatively $T_{cpu}= I \times CPI \times T_c =12000\times3.833\times0.1ns =4600 ns$

    $T_{cpu}=4.6 \mu s$ (if $f=1GHz$, $46 \mu s$)

    (c) MIPS Rate

    $MIPS = \dfrac{I}{T_{cpu}\times10^6} = \dfrac{f}{CPI\times10^6}$

    $MIPS = \dfrac{10\times10^9}{3.833\times10^6}= 2608.7$

    $\approx 2609$ MIPS $\approx 2.61\times10^3$ MIPS $=2.61$ BIPS

    Check: $MIPS =12000/(4.6\times10^{-6}\times10^6)=12000/4.6=2608.7$

    If using MIPS = I/(T in $\mu s$) same result.

    Summary: CPI $\approx 3.83$, $T \approx 4.6 \mu s$ at 10GHz ($46 \mu s$ at 1GHz), ~2609 MIPS.

15. Q4a. Explain fetch-decode-execution cycle.20147m

    Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

    Explain fetch-decode-execution cycle.

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    Fetch-Decode-Execute Cycle (Instruction Cycle)

    Every instruction goes through this cycle, driven by clock and controlled by Control Unit + SC (Sequence Counter). Also called Fetch-Decode-Execute (FDE) or Instruction Cycle.

    1. Fetch Phase

    • PC holds address of next instruction.
    • AR <- PC
    • IR <- M[AR] (Memory Read), PC <- PC+1 (point to next)
    • $T_0: AR \leftarrow PC$, $T_1: IR \leftarrow M[AR], PC \leftarrow PC+1$
    • Instruction now in IR: bits 0-11 = opcode+mode, 12-...= address. SC -> 0.
    • Micro-operations use common bus + control signals.

    2. Decode Phase

    • Control Unit decodes opcode in $IR(0-2)$ or $IR(12-14)$ depending on model, and indirect bit $I$.
    • Decodes addressing mode, determines instruction type: Memory-reference (7 ops: AND, ADD, LDA, STA, BUN, BSA, ISZ), Register-reference, I/O.
    • Generates control signals for next phase. No bus transfer, just combinational decode.
    • $T_2: D_0...D_7 \leftarrow Decode(IR_{12-14}), AR \leftarrow IR_{0-11}, I \leftarrow IR_{15}$

    3. Execute Phase

    • Performs operation specific to opcode. Different $T_3, T_4...$ micro-ops.

    Examples:

    • LDA (Load AC): $T_4: DR \leftarrow M[AR]$, $T_5: AC \leftarrow DR, SC\leftarrow0$
    • ADD: $T_4: DR \leftarrow M[AR]$, $T_5: AC \leftarrow AC+DR, E\leftarrow C_{out}, SC\leftarrow0$
    • BUN (Branch Unconditional): $T_4: PC \leftarrow AR, SC\leftarrow0$
    • Register-reference (e.g., CLA, CMA) executed at $T_3$ in one cycle.
    • Indirect cycle adds AR <- M[AR] if $I=1$ ($T_3$).

    After execute, $SC$ cleared to 0, cycle repeats for next instruction.

    Diagram / Flow

    +------+     Fetch      +------+    Decode     +--------+    Execute    +------+
    |  PC  | ------------> |  IR  | ------------> | Control| ------------> |  ALU |
    | AR   |  M[AR]->IR    |      |  opcode->D   |  Unit  |  micro-ops    |  AC  |
    | MEM  |  PC++         |      |  AR<-addr    |        |  AC<-AC+DR    |  DR  |
    +------+               +------+               +--------+  PC<-AR etc   +------+
       ^                                                                  |
       |<---------------------- SC=0, next instruction -------------------|
    

    Timing: Each phase takes 1+ clock cycles; CPI = cycles per instruction (1 for simple, 5-6 for memory-reference). Interrupts checked after Execute before next Fetch: if R=1: handle interrupt (save PC -> M[0], PC=1).

    Pipelined CPUs overlap F-D-E of successive instructions; single-cycle vs multi-cycle vs pipelined designs differ in how many clocks per phase.

16. Q4b. Differentiate between hardwired programmed control and microprogrammed control.20147m

    Module 4: Memory Organization

    Differentiate between hardwired programmed control and microprogrammed control.

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    Hardwired vs Microprogrammed Control Unit

    Aspect	Hardwired Control	Microprogrammed Control
    Principle	Control signals generated by combinational circuit (logic gates, encoder/decoder, sequence counter SC, flip-flops). Fixed wiring.	Control signals generated by microprogram stored in Control Memory (ROM). Each microinstruction bit = one control signal; execution = fetching microinstructions.
    Structure	Gates + Decoder (IR opcode -> D0-D7) + Timing $T_0..T_{15}$ from SC + Flip-flops (E, I) + Encoder to generate $S_2S_1S_0$, $LD_{AC}$ etc.	Control Address Register (CAR), Control Data Register (CDR), Control Memory (256x20 bits), Next-address logic / Sequencer, Control Buffer Register.
    Storage	No stored program. Combinational logic.	Microprogram in ROM/RAM (firmware). $n$ microinstructions per machine instruction.
    Speed	Fast (gate delay only) ~ 1-2 gate levels. Ideal for RISC, pipelined.	Slower (control memory access each microcycle, ~1 memory fetch per microinstruction)
    Flexibility	Inflexible - to change instruction set need to redesign hardware/wiring. Complex to modify.	Flexible - change by updating microcode ROM; add new instruction by adding microroutine. Easy to support CISC complex instructions.
    Design Cost	Complex design for many instructions (many states, hard to debug). But cheap hardware for simple ISAs.	Easier design: write microprogram akin to programming. Modular.
    Complexity handling	Becomes unwieldy when instructions > ~50, addressing modes many (state explosion).	Handles complex instructions (MUL, interrupt) easily - just longer microroutine. Used in CISC (IBM 360, VAX, 68000).
    Control signals	Generated as Boolean equations: e.g., $LD_{AR}= D_4T_0 + D_5T_4$	Each bit of microinstruction directly drives signal: $F_1F_2F_3, D_7..D_0$ etc.
    Modification	Requires hardware change (ECN).	Can be patched via writable control store (WCS) - firmware update.
    Example	RISC processors (MIPS, ARM), old 8085 hardwired, Mano basic computer simplified hardwired version.	Historical: IBM System/360, Intel microcode for x86 CISC, modern x86 decodes complex instructions to micro-ops from microcode ROM.
    Control memory size	None	Need $2^k \times$ width ROM; control throughput is fetch-decode of microinstructions (horizontal vs vertical microcode).
    Techniques	Sequence counter + decoder; one-hot, PLA	Horizontal (many bits per microinst, parallel) vs Vertical (encoded fields, compact) ; Wilkes model.

    Diagram Analogy

    • Hardwired: IR,T,I,SC -> Combinational Logic (PLA) -> 30 control lines
    • Microprogrammed: IR -> Map -> CAR -> Control Memory -> CDR -> control lines; CDR.next_addr -> CAR

    Horizontal vs Vertical within Microprogrammed

    • Horizontal: 40-60 bits, each bit one signal - high parallelism, fast but large ROM.
    • Vertical: 16-20 bits encoded, needs decoder, compact but slower.

    Modern hybrid: RISC core hardwired for simple ops + microcode ROM for complex x86 instructions translated to micro-ops (e.g., Intel/AMD).

    Conclusion: Use Hardwired when speed is critical and instruction set simple/small; use Microprogrammed when instruction set is complex/variable and design flexibility/upgradeability matters.

17. Q5a. Explain stack-based architecture of a CPU with the help of a diagram.20147m

    Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

    Explain stack-based architecture of a CPU with the help of a diagram.

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    Stack-Based Architecture of CPU

    Definition: A stack is a LIFO (Last-In-First-Out) storage structure where access is only at the TOP. In a stack-based CPU (0-address machine), operands are implicitly taken from the top of stack and result is pushed back onto stack. Instructions do not contain address fields for operands e.g. ADD, PUSH A, POP B.

    1. Organization

    Stack can be:

    • Register Stack: Small set of registers organized as stack (fast, limited depth)
    • Memory Stack: Reserved memory region with Stack Pointer (SP) register pointing to TOS. Grows toward lower addresses (in x86) or upward.

    Main Registers involved:

    • SP (Stack Pointer): Holds address of Top-Of-Stack (TOS)
    • TOS: Top element itself, sometimes a dedicated register for fast access
    • PC, MAR, MDR, IR as usual

    2. Diagram

                        CPU
        +-------------------------------+
        |  ALU                          |
        |   ^                           |
        |   |                           |
        |  TOS  <-- Top of Stack        |      Memory (Stack Region)
        |   |                           |      +-------------------+
        |  SP ---> [ STACK ] -----------+----> |        ...        |
        |         (LIFO)                |      |  TOS -> [  Data  ] | <- SP
        |                               |      |         [  Data  ] |
        |  MAR / MDR -------------------+----> |         [  Data  ] |
        +-------------------------------+      |        ...        |
                                             +-------------------+
                    PUSH: SP <- SP-1 ; M[SP] <- data
                    POP : data <- M[SP] ; SP <- SP+1   (for descending stack)
    

    For Register Stack (e.g. 64-word stack):

       SP -> |  A  |  <- TOS
             |  B  |
             |  C  |
             |  D  |
             |_____|
     DR --TOS-- ALU
    

    3. Operations

    • PUSH X: SP ← SP +/- 1 ; M[SP] ← X (or TOS ← X ; SP ← SP+1)
    • POP X: X ← M[SP] ; SP ← SP -/+ 1
    • ADD: TOS ← TOS + NEXT ; pop one item. Example: ADD does A← M[SP]; B← M[SP-1]; M[SP-1]← A+B; SP← SP-1

    Expression Evaluation Example: X = (A+B)*(C-D)

    PUSH A
    PUSH B
    ADD      ; TOS = A+B
    PUSH C
    PUSH D
    SUB      ; TOS = C-D
    MUL      ; TOS = (A+B)*(C-D)
    POP X
    

    4. Characteristics

    • 0-address instruction - opcode only, operand location implicit.
    • No need to specify addresses, instruction length small, code compact.
    • Hardware simplifies compiler for expression evaluation using postfix (Reverse Polish Notation).
    • Used in HP calculators, Java Virtual Machine (JVM), Burroughs B5000.

    5. Advantages & Disadvantages

    Advantages: Simple instruction format, efficient for subroutine calls (saving return address, registers), interrupt handling, easy compilation of arithmetic expressions.

    Disadvantages: Stack is bottleneck (sequential access only), random access to stack elements difficult, stack overflow/underflow must be handled, slower than register-to-register if many stack memory accesses (needs cache/TOS optimization).

    In modern CPUs, stack is used for CALL/RET, parameter passing, local variables, while general-purpose register architecture is preferred for speed.

18. Q5b. List registers of a non-pipelined CPU. Explain the purpose of each register.20147m

    Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

    List registers of a non-pipelined CPU. Explain the purpose of each register.

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    Registers of a Non-Pipelined (Single-Cycle / Multi-cycle) CPU

    In a non-pipelined CPU only one instruction is in execution at a time (fetch-decode-execute completes before next fetch). Registers are small, fast storage inside CPU.

    1. Main Register Set

    Register	Full Name	Size (typ)	Purpose
    PC	Program Counter	16/32/64-bit	Holds address of next instruction to fetch. Incremented after fetch; loaded with branch target on jump.
    IR	Instruction Register	16-32 bit	Holds current instruction opcode + operand fields after fetch. Decoded to generate control signals.
    MAR	Memory Address Register	same as address bus	Buffers address to be sent to memory. MAR ← PC for fetch, MAR ← operand address for data.
    MBR/MDR	Memory Buffer/Data Register	word size	Buffers data to/from memory. MBR ← M[MAR] on read; M[MAR] ← MBR on write. Isolates CPU from memory bus timing.
    AC	Accumulator	word size	Implicit operand and result register in accumulator machines. ALU operations: AC ← AC op MBR. Single AC minimizes address field.
    GPRs R0-Rn	General Purpose Registers	word size	Hold operands, addresses, intermediate results, loop counters. Reduce memory accesses.
    SP	Stack Pointer	address size	Points to Top-Of-Stack for PUSH/POP, CALL/RET. SP ← SP ±1 automatically.
    PSW/FLAGS	Processor Status Word / Condition Codes	8-32 bit	Flags: Z(Zero), C(Carry), N(Negative/Sign), V(Overflow), P(Parity), I(Interrupt enable). Set by ALU, tested by branches.
    Index / Base Registers	X, BR	address size	Effective address calculation: EA = BR + Index + displacement for arrays.
    Temporary / Buffer Registers	TMP, Y, Z	word size	Invisible to programmer, hold intermediate ALU inputs (e.g., TMP ← R1 ; R3 ← TMP + R2). Needed because ALU is combinational.

    Some CPUs also have: SC (Sequence Counter), AR, DR in textbook (Mano) notation.

    2. Diagram - Datapath with Registers (Non-Pipelined)

            +----+    +----+    +------+
     PC --->| MAR|-->|Memory|--->| MBR  |----> IR (opcode)
            +----+    +----+    +------+       |
               ^                  |            v
               |                  v        Control Unit
               +--------------->+-----+       |
                              | ALU |<--AC/GPRs--> Registers
                              +-----+       |
                                 |      PSW/FLAGS
                                 v
                               MDR/MAR path to memory
    

    3. Operation Flow (Example: ADD M[X])

    1. MAR ← PC ; PC ← PC+1
    2. MBR ← M[MAR] ; IR ← MBR (Fetch)
    3. Decode IR
    4. MAR ← IR(address) ; MBR ← M[MAR]
    5. AC ← AC + MBR ; Z,C,N,V updated in PSW

    All registers hold values stable for the whole cycle; non-pipelined means no overlapping - next instruction waits until write-back finishes, so no pipeline registers needed, but CPI = 1 (single-cycle, long clock) or CPI >1 (multi-cycle).

19. Q6(a). Differentiate between expansion and extension of memory.20147m

    Module 4: Memory Organization

    Differentiate between expansion and extension of memory.

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    Differentiate between Expansion and Extension of Memory

    Although both are techniques to increase memory capacity using smaller chips, they address different dimensions: depth (words) vs. width (bits). Sometimes textbooks use the terms interchangeably, but standard distinction is:

    Aspect	Memory Expansion (Word/Depth Expansion)	Memory Extension (Bit/Width Extension)
    Goal	Increase number of words (depth) e.g., $1K\times8$ -> $4K\times8$	Increase word length / bits per word (width) e.g., $1K\times4$ -> $1K\times8$
    What is increased	Address space (more addresses)	Data bus width (more bits per address)
    Address lines	Extra MSB lines needed for chip selection; address split into chip-select + intra-chip address	Same address lines to all chips; no extra address decoding for width
    Data lines	Data width unchanged; chips' data buses share via tri-state/bus, only one active at a time	Data buses concatenated; each chip contributes part of word, all active simultaneously
    Chip Select (CS) logic	Decoder required: $m$-to-$2^{m}$ decoder driven by high-order address bits enables one chip at a time	No decoder: CS of all chips tied together (common CS), all chips enabled together
    Connection	Address buses common, data buses common (wired-OR via tri-state), CS decoded	Address buses common, data buses split/combined, CS common
    Example	Four $1K\times8$ to make $4K\times8$: <br> A0-A9 to all chips, A10-A11 -> 2:4 decoder -> CS0-CS3. Data D0-D7 common bus.	Two $1K\times4$ to make $1K\times8$: <br> A0-A9 to both, CS0=CS1= CS, Chip1 D0-D3 -> system D0-D3, Chip2 D0-D3 -> system D4-D7.
    Diagram	CPU A0-A9 ----> all chips A0-A9<br>`CPU A10-A11 -> Decoder -> CS0	CS1
    Analogy	Adding more pages to a book (more pages)	Widening each page (more columns per page)

    Diagrams

    Expansion (Depth) $2K\times8$ using $1K\times8$ x2:

              A0-A9 +----------------+
          +---------->| 1Kx8 Chip0   |----> D0-D7 --+
          |           +----------------+            | Tri-state
    A0-A9-+           +----------------+            +--> System D0-D7
          +---------->| 1Kx8 Chip1   |----> D0-D7 --+
          |           +----------------+
    A10 --> Decoder -> CS0 (A10=0), CS1 (A10=1)  (only one active)
    

    Extension (Width) $1K\times8$ using $1K\times4$ x2:

    A0-A9 ------> +--------+  D0-D3 ----> System D0-D3
                  |1Kx4 C0 |
    CS   -------->|        |
                  +--------+
    A0-A9 ------> +--------+  D0-D3 ----> System D4-D7
                  |1Kx4 C1 |
    CS   -------->|        |
                  +--------+
    

    Combined: To make $4K\times16$ from $1K\times8$ chips, do both: need 4 groups (expansion) each with 2 chips in parallel (extension) = 8 chips.

    In short: Expansion = more words, Extension = wider words. Both together give arbitrary $M \times N$ memory from $m \times n$ chips.

20. Q6b. Describe organization of a typical RAM chip. Differentiate between static RAM chip and dynamic RAM chip.20147m

    Module 4: Memory Organization

    Describe organization of a typical RAM chip. Differentiate between static RAM chip and dynamic RAM chip.

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    Solution - RAM Chip Organization & SRAM vs DRAM

    A) Organization of a Typical RAM Chip:

    A RAM chip of size $2^k \times m$ (e.g., $1024 \times 8$, $16K \times 1$) has:

    • Memory Array: Matrix of memory cells arranged in rows $\times$ columns. For $1024 \times 8$, 8192 cells (128 rows $\times$ 64 columns).
    • Address Decoder: $k$ address lines decoded to select one row/word. Row decoder selects row, column decoder selects bit group. Example: 10 lines for 1024 words (5 for row, 5 for column or 10 for row).
    • Memory Cells: Each cell stores 1 bit (flip-flop for SRAM, capacitor+transistor for DRAM).
    • Chip Select (CS) / Chip Enable (CE): Enables chip only when selected - allows building larger memories by combining chips.
    • Read/Write Control (RD/WR, WE, OE): $W=0$ write enabled, $W=1$ read.
    • Bidirectional Data Lines ($I/O_{0}..I/O_{m-1}$): Input data for write, output for read - tri-state buffers. $m$ lines = word length.
    • Address Lines ($A_0..A_{k-1}$): Input address.

    Construction of larger memory: Using chip select and address decoding. Eg., to make $2K \times 8$ from two $1K \times 8$ chips, $A_{10}$ drives CS via decoder.

    Block diagram: Address Lines -> Row/Column Decoder -> Memory Cell Array -> Sense Amplifiers / Write Drivers -> Data Lines. Control logic coordinates CS, OE, WE.

    B) Difference between Static RAM (SRAM) and Dynamic RAM (DRAM):

    Parameter	Static RAM (SRAM)	Dynamic RAM (DRAM)
    Cell Design	6 transistors (bistable latch/flip-flop)	1 transistor + 1 capacitor (charge storage)
    Storage	Holds data as long as power on (static)	Charge leaks, needs periodic refresh every ~2ms
    Refresh Circuit	Not needed	Required (refresh controller, ROW strobing)
    Density	Low (6T per bit)	High (1T per bit) - 4-5x denser
    Speed	Fast (access 1-10 ns, no refresh overhead)	Slower (access 50-70 ns + refresh)
    Power	More power per cell, but no refresh power	Less per cell, but refresh consumes power
    Cost	Costly per bit	Cheap per bit
    Use	Cache (L1,L2,L3), fast buffers, registers	Main memory (DDR SDRAM)
    Volatility	Volatile (like DRAM)	Volatile

    Summary: SRAM = speed, DRAM = density & cost-effectiveness for large memory.

    Typical RAM Chip Pin Diagram: $A_0-A_9$, $D_0-D_7$, $\overline{CS}$, $\overline{WE}$, $\overline{OE}$, $V_{cc}$, $GND$.

21. Q7a. Explain swapping. Why is it used in memory management?20147m

    Module 4: Memory Organization

    Explain swapping. Why is it used in memory management?

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    Swapping in Memory Management

    Definition

    Swapping is the technique of temporarily moving a process (whole or part) from main memory (RAM) to secondary storage (swap space/backing store) and bringing it back later for execution.Introduced in early time-sharing systems (Atlas, UNIX) to support multiprogramming beyond physical memory size.

    Stored image on disk is called swap-out; retrieving is swap-in (roll-out / roll-in).

    How it Works

    1. Scheduler detects low free frames or blocked process waiting for I/O.
    2. Swapper (mid-term scheduler) selects victim process → copies its entire address space (code, data, stack, PCB) to contiguous swap area on disk.
    3. Page tables / base-limit registers updated, frames freed.
    4. Later when memory available and process scheduled, swapper reads image back (possibly at different physical address → requires relocation / dynamic binding via relocation register).

    Modern systems swap pages/segments, not whole processes (demand paging is a lazy swap).

    Diagram: Main Memory [P1|P2|P3|hole] ↔ Disk Swap Area [P4(swapped)] ↔ Scheduler

    Why Used? (Objectives)

    • Multiprogramming degree: Run more processes than fits in RAM. Example $8$ processes $\times 200KB =1.6MB$ on $1MB$ RAM via time-multiplexing.
    • Memory compaction / fragmentation removal: Swapping out creates large contiguous free blocks, reducing external fragmentation.
    • Priority & scheduling: Swap out low-priority/blocked processes to give room to urgent ones (mid-term suspend).
    • Fairness & time-sharing: Quantum expired → swap out to let next process in.
    • Emergency handling: Low-memory handler frees RAM quickly.
    • I/O overlap & backing store for paging: Pages not resident stay on disk.

    Types

    • Whole-process swapping: Simple but heavy I/O (entire address space).
    • Page swapping (paging): Swap only pages, more efficient, foundation for virtual memory.
    • Segment swapping: Similar for segmented systems.

    Cost & Issues

    • Transfer time: Main cost $T_{swap}=2\times (size/transfer-rate) + seek/latency$. e.g. $10MB/100MBps=100ms$. So swap only if process idle for longer.
    • Blocked I/O: Process with pending I/O or pinned pages cannot be swapped.
    • Thrashing risk: Excessive swapping degrades CPU utilization → need working set / locality.

    Today pure swapping rare; virtual memory + demand paging is generalized swapping with finer granularity, and swap file/partition remains as overflow store.

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23. Q7b. Explain virtual memory. Explain the role of logical as well as physical address.20147m

    Module 4: Memory Organization

    Explain virtual memory. Explain the role of logical as well as physical address.

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    Virtual Memory

    Definition: Virtual memory is a memory management technique that makes an application think it has contiguous, large private address space, independent of physical RAM size, by automatically moving data between RAM and disk (swap/backing store) via paging/segmentation. It gives illusion of virtual size >> physical size.

    OS + MMU provide address translation per reference; only active working set stays in RAM, rest on disk, loaded on demand (page fault).

    Why Virtual Memory?

    • Run programs larger than physical memory.
    • Multiprogramming isolation & protection (each process virtual space).
    • Simplified linking/loading, no external fragmentation (with paging).

    Logical (Virtual) vs Physical Address - Roles

    Logical / Virtual Address - Generated by CPU before translation.

    • Address seen by process/compiler: e.g. $32$-bit virtual → $4GB$ per process ($2^{32}$), $48$-bit in x86-64.
    • Partitioned: | Virtual Page Number (VPN) | Offset | (offset = page size bits; e.g. $4KB$ page → $12$ bits offset).
    • Never used to access RAM directly; goes through MMU.
    • Contiguous from process view; sparse vs file mapping allowed.
    • Protect bits checked per virtual page.

    Physical Address - Actual address on RAM bus after translation.

    • After MMU/TLB lookup: | Physical Frame Number (PFN) | Offset |.
    • Range limited by installed RAM: e.g. $1GB$ RAM → $30$-bit physical.
    • Used by cache/memory controller.
    • Multiple virtual pages (even from different processes) can map to same physical frame (shared memory) or one virtual page can map nowhere (paged out → page fault).

    Translation flow:

    CPU issues VA ──► TLB (VPN→PFN) hit? ──► PA to cache/RAM
                      │ miss
                      └─► Page Table walk (in RAM) ──► PFN + valid bit
                                   │ invalid (not resident)
                                   └─► Page Fault → OS loads frame from disk, updates table, retries
    

    Example: VA 0x00403F12 ($VPN=0x403, offset=0xF12$) with $4KB$ pages, page table maps $VPN\ 0x403 → PFN\ 0x1A2$ → PA 0x1A2F12.

    Key distinction: Logical addresses give program portability & protection; physical addresses give actual storage location. Compiler/linker deals in logical; MMU/OS manages physical. Without translation, process would see raw RAM limits and fragmentation.

    Modern extensions: Demand paging, copy-on-write, memory-mapped files, TLB, multi-level page tables all build on this split.

24. Q8. Explain the use of DMA controllers in a computer system with a neat diagram.201414m

    Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

    Explain the use of DMA controllers in a computer system with a neat diagram.

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    DMA Controller

    DMA controller is a dedicated hardware module that manages direct memory ↔ I/O transfers without CPU per-word involvement.

    Block Diagram (textual):

     CPU ── Address/Data/Control Bus ─┬─ Main Memory
           ┌──────────────┐            ├─ DMA Controller ── I/O Device(s)
           │  CPU         │--HOLD/BR-->│ Address Reg (AR)   │
           │              │<--HLDA/BG--│ Count Reg (WC)     │-- DREQ/DRQ ← Device
           └──────────────┘            │ Control Reg        │-- DACK → Device
                                       │ Data Buffer        │-- IRQ → CPU
                                       │ Bus Arbiter        │
                                       └──────────────┘
    

    Internal components: Address Register (current memory address, auto-incremented), Word Count Register (down-counter), Control/Status Register (R/W direction, transfer mode, enable, interrupt enable flag), Data Buffer/Latch, Bus Control Logic.

    Use in System:

    1. CPU programs DMA: loads AR = start address, WC = block size, Control = read/write, burst vs cycle-steal, channel priority. Enables DREQ mask.
    2. CPU issues I/O command to peripheral, then continues program.

    Operation:

    • Peripheral asserts DRQ when ready for word.
    • Controller asserts HOLD / Bus Request to CPU.
    • CPU finishes current machine cycle, floats buses, asserts HLDA / Bus Grant.
    • Controller drives address from AR onto address bus, generates MEM RD/WR and I/O RD/WR, transfers word via buffer. AR++, WC--.
    • If WC≠0 and cycle-steal mode, releases HOLD for one cycle and reacquires next transfer; in burst mode holds bus until WC=0.
    • When WC=0 → Terminal Count (TC) → controller deasserts HOLD, asserts Interrupt (IRQ) to CPU, sets DONE bit.

    Modes: Single transfer, Block/Burst, Demand/Cascade (8237 A has 4 channels, chained). Advantage: For $n$-word block only one interrupt, bandwidth near memory bandwidth (~MB-GB/s) instead of ISR per word.

    Multichannel controllers include priority resolver (fixed/rotating) for multiple devices arbitrating for DMA.

25. Q9. Explain handshake protocol. Depict clearly how it controls data transfer during an input operation.201414m

    Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

    Explain handshake protocol. Depict clearly how it controls data transfer during an input operation.

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    Handshake Protocol – Input Operation Control (14 Marks)

    Defines asynchronous handshaking to transfer data from input device to CPU/memory without common clock, ensuring data is not lost when device and CPU speeds differ.

    Principle: Two control lines: DATA VALID (source says data ready) and DATA ACCEPTED / ACK (destination says data captured). Both sides interlock.

    Destination-Initiated Handshake for Input (CPU reading from device):

    This is typical for input – CPU/destination initiates because it knows when it can accept.

    Steps with timing:

    1. Idle: Data bus invalid, VALID=0, ACCEPT=0, Ready=0
    2. Destination (CPU interface) is ready to receive → asserts READY / REQUEST (or ACCEPT high)
    3. Input device places data byte on data bus (e.g., keyboard, ADC) and after settling asserts DATA VALID / STROBE
    4. Destination latches data into input buffer register on seeing VALID, then asserts DATA ACCEPTED / ACK =1
    5. Device sees ACK, deasserts VALID =0 and removes data from bus
    6. Destination sees VALID low, deasserts ACK/READY =0, handshake cycle complete, next data can be requested

    Sequence diagram:

    Device:  ----data valid---->
    CPU:     <--- ack --------
    Time:  Req↑ → Data→ Valid↑ → Latch → Ack↑ → Valid↓ → Ack↓
    

    Source-Initiated alternative: Device asserts VALID first (if data arrives spontaneously), CPU responds with ACK after reading. Used for interrupts.

    Hardware Control:

    • Device side: Data register + Valid flip-flop
    • CPU side: Buffer register + Ready/Ack logic + Interrupt/DMA request
    • Example: 8255 PPI Handshake Input Mode – STB (strobe input, active low from device), IBF (Input Buffer Full to device), INTR to CPU. Device pulses STB after putting data, IBF goes high acknowledging latch, CPU reads port resetting IBF.

    Advantages: No clock correlation needed, reliable at any speed, automatic flow control.
    Disadvantage: Extra 2-wire overhead and handshake delay lowers max throughput; need 4-phase protocol for reliability.