2015 question paper

COMPUTER ORGANIZATION & ARCHITECTURE

17 questions

Q1a. What is the difference between Programmed I/O and Interrupt-driven I/O?20152m

Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

What is the difference between Programmed I/O and Interrupt-driven I/O?

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Worked Solution

Difference: Programmed I/O vs Interrupt-driven I/O (2 marks, ~120 words)

Feature	Programmed I/O	Interrupt-driven I/O
CPU involvement	CPU polls status register continuously (busy-wait)	CPU continues other work; device interrupts when ready
Efficiency	Wasteful - CPU idle in loop	Efficient - no polling
Hardware	No interrupt logic needed	Needs interrupt controller, vector, enable/disable
Response time	Slower for infrequent devices	Faster, immediate via ISR
Use case	Simple, low-speed transfers	Better for multiple / faster devices

Summary: Programmed I/O = synchronous polling; Interrupt-driven I/O = asynchronous, CPU is freed until interrupt signals data ready, then CPU vectors to ISR to handle transfer.

Q1b. Explain different types of interrupts.20152m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
Explain different types of interrupts.

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Worked Solution
Types of Interrupts:

Hardware vs Software Interrupt:

Hardware Interrupt: Generated externally by hardware devices (e.g., I/O device, timer) signalling CPU via INTR/NMI pins. Asynchronous to program.

Software Interrupt: Generated internally by executing INT n instruction. Synchronous, used for system calls and exception handling.

Maskable vs Non-Maskable Interrupt:

Maskable (INTR): Can be enabled/disabled by Interrupt Flag (IF). CPU can ignore if IF=0. Used for normal peripherals.

Non-Maskable (NMI): Cannot be disabled, always serviced (IF has no effect). For critical events like power failure, memory parity error.

Vectored vs Non-Vectored Interrupt:

Vectored: Interrupting device supplies vector address (branch address) directly. No polling needed. e.g., Intel RST, TRAP.

Non-Vectored: Vector address not supplied; CPU must poll/interrogate devices or jump to fixed address to identify source and then branch.
Q1c. Describe the phases in an instruction cycle.20152m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
Describe the phases in an instruction cycle.

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Worked Solution
Instruction Cycle Phases:

Fetch (F): Address in PC is put on bus, instruction fetched from memory to IR, PC incremented to next instruction.

Decode (D): Control unit decodes opcode in IR, identifies instruction type, operand addressing modes, and generates control signals; operands fetched from registers.

Execute (E): ALU/Control performs operation - arithmetic/logic, effective address calculation, branch target evaluation.

Memory/Interrupt Check: If instruction needs memory access (LOAD/STORE) data transfer occurs; finally CPU checks for pending interrupts - if any, save context and branch to ISR.

Cycle repeats as: $Fetch \rightarrow Decode \rightarrow Execute \rightarrow Interrupt\ Check$ .
Q1c. Define program counter.20152m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
Define program counter.

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Worked Solution
Program Counter (PC):

The Program Counter is a CPU register that holds the memory address of the next instruction to be fetched for execution.

At fetch, CPU reads instruction from address in PC, then PC is incremented (by instruction length, typically +1 or +4) to point to next sequential instruction.

On branch/jump/call/return and interrupt, PC is loaded with target address, changing sequential flow.

Essential for control flow and instruction sequencing; often called Instruction Pointer (IP).

Also used to calculate return address and for relative addressing.
Q1e. What do you mean by direct memory access?20152m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
What do you mean by direct memory access?

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Worked Solution
Direct Memory Access (DMA):

Technique that allows an I/O device to transfer data directly to/from main memory without CPU intervention for each word.

DMA controller (DMAC) takes over system buses (via Bus Request BR / Bus Grant BG, cycle stealing or burst mode).

CPU initializes DMAC with start address, word count and direction; DMAC then handles the entire block transfer.

CPU is free to do other work; interrupted only at start and completion.

Advantage: Much faster than programmed or interrupt-driven I/O for high-speed devices (disk, display) — especially for large block transfers.

Q1f. What is the difference between hardwired control and microprogrammed control?20152m

Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

What is the difference between hardwired control and microprogrammed control?

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Worked Solution

Hardwired vs Microprogrammed Control:

Hardwired Control	Microprogrammed Control
Uses combinational logic, gates, flip-flops, decoders - physically wired	Uses microcode stored in Control Memory (control store) - sequence of micro-instructions
Fast - propagation delay only	Slower - needs microinstruction fetch from control store
Difficult to modify - requires hardware redesign to add new instruction	Easy to modify - just change microcode
Complex design for complex ISA (large, inflexible)	Suitable for complex CISC, easy implementation of complex instructions
RISC typically uses hardwired	CISC (IBM 360, x86) often uses microprogrammed
No control memory needed	Requires control memory, MPC, microinstruction sequencer

In short: Hardwired = speed, inflexible; Microprogrammed = flexibility, slower, easy to extend.

Q1g. What is the importance of cache memory in a computer?20152m
Module 4: Memory Organization
What is the importance of cache memory in a computer?

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Importance of Cache Memory (2 Marks)

Cache is a small, very fast SRAM between CPU and main memory that bridges the speed gap between high-speed processor and relatively slow DRAM main memory.

Speed Gap: CPU cycle time is ~1ns while DRAM access is ~50-100ns. Without cache, CPU would stall waiting for memory. Cache (access ~2-5ns) supplies most needed words at CPU speed.

Exploits Locality of Reference: Due to temporal locality (recently used data reused soon) and spatial locality (next addresses likely accessed), ~90-95% accesses hit in cache, giving average access time ≈ cache time.

Result: Improves effective memory access time, increases throughput, reduces memory bandwidth demand. Hence hit ratio and system performance increase significantly despite small size and high cost/bit.
Q1h. Briefly explain subroutine call and return.20152m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
Briefly explain subroutine call and return.

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Subroutine Call / Return Mechanism (2 Marks)

Uses stack to save return address and transfer control:

CALL (Call Subroutine):

Push return address: SP ← SP - 1; M[SP] ← PC (PC holds next sequential address after CALL)

Jump to subroutine: PC ← effective address of subroutine (branch target)

Assembly: CALL 2050H does above in one micro-sequence.

RET (Return):

Pop return address: PC ← M[SP]; SP ← SP + 1

Fetch resumes at saved location.

Stack LIFO supports nesting: each CALL pushes new address, each RET pops in reverse order, enabling recursion. Link register variant saves PC in LR instead of memory stack for low-overhead leaf calls.

Q1i. What do you mean by array processors? How are they different from scalar processors?20152m

Module 3: Pipelining

What do you mean by array processors? How are they different from scalar processors?

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Array Processor (Vector Processor):
An array processor is a processor that performs the same operation on multiple data elements simultaneously. It is designed for vector/array computations (matrix operations, image processing, scientific computing). It implements SIMD - Single Instruction Multiple Data architecture (Flynn's taxonomy). Example: ILLIAC-IV, BSP, GPU vector units, Intel AVX.

It consists of a single Control Unit and multiple Processing Elements (PEs)/ALUs working in parallel under common control.

Scalar Processor:
A scalar processor processes one data item at a time per instruction. It executes one instruction on one operand pair sequentially. It implements SISD - Single Instruction Single Data. Example: Conventional Intel 8086, basic RISC core. To process an array of N elements, scalar must loop N times.

Difference - Array vs Scalar (SIMD vs SISD):

Aspect	Array (SIMD)	Scalar (SISD)
Parallelism	Data parallelism, N PEs operate concurrently	No data parallelism, sequential
Instruction	One instruction controls many ALUs	One instruction → one ALU operation
Performance	High throughput for vector tasks, $Speedup \approx N$	Lower for vector tasks, loop overhead
Use	Scientific, MATLAB, ML, graphics	General purpose
Cost/Complexity	Higher hardware, interconnection network needed	Simpler control

In short, array processor exploits DLP to compute C[i]=A[i]+B[i] in one step; scalar needs N iterations.

Q2. Explain in detail the different addressing modes.201514m

Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

Explain in detail the different addressing modes.

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Addressing Modes - Detailed Explanation [14 Marks]

Addressing mode defines how the effective address (EA) of an operand is generated from the instruction. It determines where the operand is - in instruction itself, register, or memory. Efficient modes reduce instruction size and execution time.

1. Implied / Implicit Mode

Operand is implied by opcode itself. No address field.
Example: CLC (clear carry), HLT, STC. EA not needed.

2. Immediate Mode

Operand is literal value within instruction.
EA = - , Operand = instruction field

MOV AL, #20H    ; AL <- 20H
ADD R1, #10     ; R1 <- R1 + 10

Advantage: Fast (no memory fetch for operand). Use: constants.

3. Register Mode

Operand in CPU register. Field specifies register number.

MOV R1, R2      ; R1 <- R2
ADD AX, BX

Very fast - no memory access. Register Indirect variant: register holds memory address.

MOV AL, [BX]    ; AL <- M[BX]   (BX points to memory)
LDA (R1)        ; AC <- M[R1]

4. Direct / Absolute Mode

Instruction contains full memory address of operand.
EA = Address field , Operand = M[EA]

LDA 2500H       ; AC <- M[2500H]
STA 3000H

Simple but needs large address field → long instruction, limited addressability.

5. Indirect Mode

Address field contains address of address. Need two memory accesses.
EA = M[Address field]

LDA @2000H      ; If M[2000H]=3000H, then AC <- M[3000H]
MOV R1, @(R2)   ; variant: register indirect with indirection bit

Useful for pointers, but slower.

6. Indexed Mode

EA = Base (in address field) + Index Register

LDX 1000H(X2)   ; EA = 1000H + X2 , AC <- M[EA]

Variants: Auto-index (increment/decrement after access) for arrays/loops.
Use: Array access A[i] → base address of A + i.

7. Based / Base-Register Mode

EA = Base Register + Displacement

MOV AL, [BX+500H]  ; EA = BX + 500H (8086 based mode)

Similar to indexed but base is pointer (e.g., base of array/structure), displacement is offset.

8. Relative / PC-Relative Mode

EA = PC + Displacement (offset relative to current instruction)

BEQ  20H       ; branch to PC+20H if equal
JMP  LABEL     ; LABEL is displacement from PC

Advantage: Position-independent code, short displacement field.

9. Stack Mode

Operand on top of stack (SP points to TOS). Implicit.

PUSH AX       ; SP--, M[SP] <- AX
POP BX        ; BX <- M[SP], SP++

10. Autoincrement / Autodecrement (Register Indirect with update)

MOV (R1)+, R2   ; R1 points to operand, then R1++
MOV -(R1), R2   ; R1--, then access

Efficient for traversing arrays/strings.

Comparison Table:

Mode	EA Generation	Memory Accesses	Example
Immediate	No EA	0	`ADD #5`
Direct	EA = A	1	`LOAD 100`
Indirect	EA = M[A]	2	`LOAD @100`
Register	EA = R	0	`ADD R1,R2`
Reg Indirect	EA = (R)	1	`LOAD (R1)`
Indexed	EA = A + (XR)	1	`LOAD 100(X1)`
Relative	EA = PC + Offset	1	`BNE -10`

Significance in Instruction Design: Choice affects instruction length, number of memory references, capability for relocatable code, handling of arrays/pointers, and pipeline efficiency. Modern RISC (e.g., ARM, MIPS) favors register, immediate, base+offset, and PC-relative; CISC (x86) supports rich set of modes.

8086 Example: MOV AX, [BX+SI+1000H] uses based-indexed with displacement: EA = (BX)+(SI)+1000H.

Effective addressing is hardware implemented via 2's complement adder in address generation unit before memory access.

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Q3. Explain in detail the hierarchical memory structure with a neat and labelled diagram.201514m
Module 4: Memory Organization
Explain in detail the hierarchical memory structure with a neat and labelled diagram.

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Worked Solution
Hierarchical Memory Structure

Memory is organized as a pyramid/hierarchy based on trade-off between speed - cost - capacity - access time. Faster memory per bit is costlier and smaller.

↑ Speed, Cost/bit | Capacity ↓ +-----------------+ | CPU Registers | < 1 ns, <1KB, fastest, costliest +-----------------+ | Cache | L1: 2-5 ns, 32-64KB | L1 | L2 | L3 | L2: 5-10 ns, 256KB-8MB SRAM +-----------------+ | Main Memory | 50-100 ns, 4-32 GB, DRAM | (Primary) | +-----------------+ | Secondary | 5-10 ms, 256GB-4TB | SSD / HDD | +-----------------+ | Tertiary / | sec-min, TB-PB, Optical Tape | Off-line | Archival, slowest, cheapest +-----------------+ ↓ Slower, Cheaper, Larger

Levels in Detail

1. Registers (Top)

Inside CPU, <32-64 words, flip-flops, 0.5-1 ns, directly accessed by ALU.

2. Cache Memory (SRAM)

Between CPU and RAM. Holds copies of frequently used blocks (locality of reference).

L1 split I/D, L2 unified, L3 shared. Hit ratio ~ 90-95%. Block size 32-128B.

Managed by hardware.

3. Main Memory (DRAM)

Primary memory, volatile, 4-32 GB. Byte-addressable. Managed by OS + MMU.

4. Secondary (Magnetic/Flash)

Non-volatile, virtual memory backing store, page file on SSD/HDD.

5. Tertiary/Offline

Tape libraries, optical jukebox for backup.

Key Principles

Inclusion: Data at level $i$ is subset/copy of level $i+1$ (Cache contains copy of RAM block).

Locality: Temporal (recently used reused) & Spatial (neighbors used) → hierarchy works.

Access time: $T_{eff}= H\times T_{cache} + (1-H)\times (T_{cache}+T_{main})$ where $H$ is hit rate.

Cost: $C_{avg}= \frac{\sum C_i S_i}{\sum S_i}$

Advantages: Gives illusion of large, cheap memory with speed near registers; transparent to programmer via memory management; exploits locality.

Modern example PC: Registers ~1KB, L1 64KB, L2 512KB, L3 8MB, RAM 16GB, SSD 1TB, HDD/Cloud TB.
Q4. What is swapping and how is it useful in memory management?201514m
Module 4: Memory Organization
What is swapping and how is it useful in memory management?

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Swapping and Use in Memory Management

Definition

Swapping is moving a process (or part) temporarily out of main memory (RAM) to secondary storage (backing store / swap space on disk) and bringing it back later for execution. Introduced for multiprogramming when RAM insufficient.

Swap Out: RAM --> Disk; Swap In: Disk --> RAM. Managed by medium-term scheduler (swapper) and dispatcher.

How Swapping Works

System keeps Ready Queue of processes in memory and Swap Device queue on disk.

When memory pressure high or process blocked (e.g. I/O wait) and higher priority process arrives, dispatcher selects victim (e.g. lowest priority, sleeping).

Victim's entire address space (or at least resident pages) is copied to swap file, its PCB updated (state = swapped, location = disk), frames freed.

Later when memory free or process becomes ready, swapper selects swapped process, finds contiguous / non-contiguous free frames, loads it back, possibly at different physical address (requires relocation via base-limit registers or paging).

Time = swap size / transfer rate. E.g. 10 MB process, disk 20 MB/s => 0.5s out +0.5s in =1s overhead -> swapping is expensive, attempted only when needed.

Types

Whole process swapping (old UNIX, embedded) - simple but costly.

Page swapping / paging (modern VM) - swap only pages/frames, not whole process.

Roll in / Roll out for priority scheduling.

Usefulness / Advantages

Degree of Multiprogramming: Allows more processes than fits in RAM to co-exist by multiplexing memory over time, increasing CPU utilization.

Handles Insufficient Memory: Large process (>RAM) can still run by swapping parts; avoids need for all processes to fit simultaneously.

Compaction: Swapping out creates holes, allows memory compaction to reduce external fragmentation (combine free blocks) and allocate contiguous memory.

Priority Scheduling: High priority process swapped in quickly by swapping out low priority.

I/O Idle Utilization: Blocked process swapped out so its RAM used by ready processes.

Foundation for Virtual Memory: Modern demand paging is refined swapping per page with lazy loading.

Disadvantages / Considerations

Swap time overhead and disk I/O bottleneck; double transfer.

Need for relocation hardware.

Not suitable for real-time if swap time unpredictable.

Thrashing if swapped too frequently.

Requires swap space reservation on disk.

Swapping vs Paging

Swapping Paging (demand)

Whole process moved Only required pages moved

Contiguous allocation needed Non-contiguous frames ok

High overhead Lower per-fault overhead

Effective only if combined with compaction and medium-term scheduling; modern OS uses swapping + virtual memory so that Total Logical Memory >> Physical RAM.

Diagram:

Main Memory Disk (Swap Space) [ P1 ][hole][ P2 ] swap out P2 --> [P2 image] [ P1 ][ P3 ][hole] <-- swap in P4 [P4 image][P2]

Free frames consolidated after swap.
Q5. How does a DMA controller work? Explain with an example.201514m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
How does a DMA controller work? Explain with an example.

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DMA Controller - Operation

Need: Programmed I/O and Interrupt I/O keep CPU busy for each word transfer. For high-speed devices (disk, ~1MB/s) CPU waste is large. DMA allows direct memory access without CPU intervention.

DMA Controller (DMAC) - e.g., 8237 sits between I/O and system bus. It is a slave to CPU for initialization and becomes master for transfer.

Architecture

Address Register + Address Counter: Holds memory address, auto-increment/decrement.

Word Count Register: Number of words to transfer.

Control Register: Mode (read/write), burst/cycle-steal, etc.

Data Buffer, Bus Control Logic, Interrupt Logic

Working Steps

Initialization (CPU as master): CPU writes via I/O instructions - starting address -> Address Reg, count -> WC Reg, control word -> Control Reg, I/O device address.

DMA Request: I/O device ready asserts DRQ (DMA Request) to DMAC.

Bus Request: DMAC asserts HOLD (or BR) to CPU.

Bus Grant: CPU finishes current bus cycle, tristates buses, asserts HLDA (BG).

Transfer: DMAC puts DACK to device and MEM_RD/WR, IO_RD/WR, controls buses, 1 word per DMA cycle. WC--, Address++.

Burst Mode: Holds bus until count=0

Cycle Steal: Releases bus after each word

Transparent: Only during CPU idle cycles

Termination: When WC = 0, DMAC asserts TC (Terminal Count), deasserts HOLD, interrupts CPU.

During transfer CPU is idle or can execute internal operations if buses not needed.

Example: Disk -> Memory (1KB)

CPU: MOV #1000, WC ; MOV #2000H, ADDR ; MOV #READ|BURST, CTRL
Disk controller seeks sector, asserts DRQ. DMAC acquires bus.
For 1000 cycles: DMAC: Address 2000H -> Address Bus, MEM_WR, Disk RD, word transferred, WC decremented. After 1000 words, interrupt CPU -> CPU verifies status.

Diagram: CPU - System Bus (Address/Data/Control) - DMAC - I/O Device, with HOLD/HLDA, DREQ/DACK, IOR/IOW, MEMR/MEMW.

Advantage: ~100x faster than programmed I/O, CPU free for other tasks.
Disadvantage: Cache coherence issue (stale data), bus contention.
Q6. Define paging in memory management and write its advantages.201514m
Module 4: Memory Organization
Define paging in memory management and write its advantages.

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Paging in Memory Management

1. Definition

Paging is a non-contiguous memory allocation technique that eliminates external fragmentation. It divides both logical (virtual) address space and physical memory into fixed-size blocks:

Pages: Fixed-size blocks of logical/virtual memory (e.g., 4 KB)

Frames (Page Frames): Same-size blocks of physical memory

Page Table: Data structure maintained by OS that maps page number -> frame number. Each process has its own page table base register (PTBR).

Logical address = $(p, d)$ where $p$ = page number (index into page table), $d$ = offset within page.

Physical address = $(f, d)$ where $f$ = frame number from page table entry.

Translation:

Logical Addr (e.g., 16-bit with 1K page): | page p | offset d | | |-------> offset passes unchanged v Page Table[p] -> frame f | Physical Addr = f * page_size + d

With TLB (Translation Lookaside Buffer) caching recent translations for speed.

Example: Page size 4KB, 32-bit VA: 20-bit $p$ , 12-bit $d$ . Logical addr 0x00403ABC : $p=0x00403$ , $d=0xABC$ -> if PageTable[0x00403]=0x07F1A then physical = 0x07F1AABC.

If page not in memory, page fault occurs - OS loads page from disk (demand paging, virtual memory).

2. Diagram

Process Virtual Memory Page Table Physical Memory +---------------+ +------------+ +---------------+ | Page 0 |-------------->| Frame 2 |------------>| Frame 0 | +---------------+ +------------+ +---------------+ | Page 1 |-------------->| Frame 5 |------------>| Frame 1 | +---------------+ +------------+ +---------------+ | Page 2 | | invalid | | Frame 2: Pg0 | +---------------+ +------------+ +---------------+ | Page 3 |-------------->| Frame 1 | | Frame 3 | +---------------+ +------------+ +---------------+ Frame 5: Pg1

3. Advantages of Paging

No External Fragmentation: Any free frame can be allocated to any page; memory is used efficiently. Compaction not needed.

Supports Virtual Memory: Allows process size > physical memory via demand paging; only needed pages loaded, rest on disk.

Simplifies Memory Management: Fixed-size blocks easy to manage with free-frame list; allocation/deallocation fast.

Allows Sharing: Shared pages (common code/libraries) can map to same frame in different processes - saves memory.

Memory Protection: Page table entry contains protection bits (R/W/X, user/supervisor) - prevents illegal access; invalid entries cause trap.

Supports Multiprogramming: Multiple processes can reside in fragmented physical frames simultaneously.

Efficient Swapping: Swapping whole pages is easy; copy-on-write optimization possible.

Disadvantage (for completeness): Internal fragmentation (last page may be partially unused ~ half page average), and page table overhead (+ TLB needed) and extra memory reference if TLB miss (2 accesses).
Q7. Explain in detail daisy-chain priority interrupt.201514m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
Explain in detail daisy-chain priority interrupt.

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Daisy-Chain Priority Interrupt

A method to resolve simultaneous interrupt requests and assign priority by hardware wiring rather than polling software.

1. Principle

All interrupt sources are serially connected (daisy-chained) on an Interrupt Acknowledge (INTA) line from CPU.

Higher priority device is placed electrically nearer to CPU.

When CPU acknowledges interrupt (INTA=1), signal propagates sequentially.

First requesting device blocks propagation and places its vector address on bus; lower priority devices never see INTA.

2. Hardware Structure

CPU INTR ← OR of all INT requests CPU INTA → Device0 PI → Device1 PI → Device2 PI → ... Device0 PO ─┘ Device1 PO ─┘ (Device with PI=1, PO=0 handles interrupt)

Each interface contains:

Interrupt flip-flop (sets when device requests),

PI (Priority In) / PO (Priority Out) logic: PO = PI · ¬(INT_request),

Vector address generator / tri-state buffer enabled only when PI·INT·INTA.

3. Operation Sequence

One or more devices set INT.

CPU finishes current instruction, checks INTR, if enabled pushes PC/PSW, disables further interrupts, asserts INTA.

INTA ripples: Device0 check: if it requested, it clears its flag, asserts PO=0 (blocks chain), puts VAD on data bus; CPU reads vector → ISR address.

If Device0 not requesting, it passes PO=1 (=PI) to next device; same logic repeats.

ISR at end executes RETI, restores state.

4. Priority Assignment

Physical order = priority. No extra encoder needed. Typical max $5\text{-}8$ devices per chain; longer chain adds propagation delay (~10-20 ns/gate).

5. Advantages / Disadvantages

Advantages:

Simple, cheap, scalable, no polling overhead.

Automatic priority resolution in one INTA cycle.

Vectored interrupt possible per device.

Disadvantages:

Priority fixed by wiring (re-cabling to change).

Chain delay limits number of devices.

Single fault breaks chain (can be solved with open-collector / bypass cap).

Starvation of low priority devices.

6. vs Other Methods

Polling: Software tests each flag sequentially - slower but flexible.

Parallel priority encoder / Arbiter: Faster, programmable priority but more hardware.

Daisy-chain is widely used in e.g. 8085 RST 7.5/6.5/5.5, VME bus, and legacy peripheral chains.
Q8. Explain in detail the three mapping procedures related to cache memory.201514m
Module 4: Memory Organization
Explain in detail the three mapping procedures related to cache memory.

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Cache mapping decides how a main memory block maps to cache line(s). Let cache have $2^c$ lines, memory have $2^m$ blocks, address = Tag + Index/Set + Word/Offset.

1. Direct Mapping

Each memory block $i$ maps to exactly one cache line: $line = i \mod (\text{no. of lines})$ .
Address split: $|Tag| + |Line| + |Word|$ .
e.g., 4096 lines need 12 line bits. With 64-word blocks (6 bits), address = Tag(remaining)+12+6.

Search: Compare only that line's tag - fast, simple.

Miss: Replacement is forced, no choice.

Drawback: Thrashing - two blocks mapping to same line continuously collide even if cache has free lines.

2. Associative (Fully Associative) Mapping

Any memory block can go to any cache line. Address = $|Tag| + |Word|$ only; no line field.

Search: Content-addressable memory (CAM) compares incoming Tag with all line tags in parallel.

Replacement: Need algorithm - LRU, FIFO, Random.

Advantage: No collision thrashing, best hit rate.

Drawback: Expensive comparators for all lines, slow for large cache.

3. Set-Associative Mapping

Compromise. Cache divided into $S$ sets, each set has $k$ lines ( $k$ -way). Block $i$ maps to $set = i \mod S$ , can occupy any of $k$ lines within set.

Address: $|Tag| + |Set| + |Word|$ .
Example $k=2$ , 4096 lines → 2048 sets → 11 set bits. Address = Tag+11+6.

Search: Index set via Set field, associatively compare Tag among $k$ lines in that set only.

Replacement: Choose within set (LRU).

Special cases: $k=1$ → Direct, $k = \text{no. of lines}$ → Fully Associative.

Tradeoff: Hit rate improves with larger $k$ but cost increases. Typical $k=2,4,8$ .

Replacement policies (LRU, LFU, FIFO) apply to associative and set-associative when set is full. Write policies: Write-through + write-allocate/no-allocate, Write-back.
Q9. Explain in detail the handshake protocol of asynchronous data transfer201514m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
Explain in detail the handshake protocol of asynchronous data transfer

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Handshake Protocol of Asynchronous Data Transfer (14 Marks)

Asynchronous transfer is used when source and destination have different speeds/clocks, without common clock. Handshake uses control signals (Ready/Valid/Acknowledge or STROBE/ACK) to synchronize.

Need: Strobe method (single control pulse) is not reliable – source doesn't know if destination accepted data. Handshake solves by two-way signaling.

Two Types:

1. Source-Initiated (Unidirectional):
Sequence:
a) Source places data on bus
b) Source asserts Data Valid / STROBE
c) Destination accepts data, asserts Data Accepted / ACK
d) Source deasserts Data Valid after seeing ACK
e) Destination deasserts ACK – ready for next cycle

Timing diagram: Data → Valid ↑ → ACK ↑ → Valid ↓ → ACK ↓

2. Destination-Initiated:
Used when destination requests data (e.g., input device).
a) Destination asserts Request Data / Ready to Receive
b) Source places data and asserts Data Valid
c) Destination accepts and deasserts request / asserts ACK
d) Source deasserts Valid, etc.

Full Handshakes:

2-Edge (Non-Interlocked) vs 4-Edge (Fully Interlocked): 4-edge uses both rising and falling edges as events (request high → ack high → request low → ack low) – more reliable, used in buses.

Application: In CPU-I/O interface: CPU addresses device, device asserts ACK when ready; Data transferred over bus with MSTRB/SLVACK. Example: 8085 handshaking with STB, IBF in 8255 PPI mode 1.

Advantages: Speed independent, reliable, no clock skew.
Disadvantage: Extra handshake time reduces throughput vs synchronous burst.

Block diagram: Source register → Bus → Dest register with two control lines between controllers. Sequence controlled by handshake controller FSMs on both sides.

Swapping	Paging (demand)
Whole process moved	Only required pages moved
Contiguous allocation needed	Non-contiguous frames ok
High overhead	Lower per-fault overhead

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COMPUTER ORGANIZATION & ARCHITECTURE

1. Implied / Implicit Mode

2. Immediate Mode

3. Register Mode

4. Direct / Absolute Mode

5. Indirect Mode

6. Indexed Mode

7. Based / Base-Register Mode

8. Relative / PC-Relative Mode

9. Stack Mode

10. Autoincrement / Autodecrement (Register Indirect with update)

Pocketly on Android

Hierarchical Memory Structure

Levels in Detail

Key Principles

Swapping and Use in Memory Management

Definition

How Swapping Works

Types

Usefulness / Advantages

Disadvantages / Considerations

Swapping vs Paging

DMA Controller - Operation

Architecture

Working Steps

Example: Disk -> Memory (1KB)

Paging in Memory Management

1. Definition

2. Diagram

3. Advantages of Paging

Daisy-Chain Priority Interrupt

1. Principle

2. Hardware Structure

3. Operation Sequence

4. Priority Assignment

5. Advantages / Disadvantages

6. vs Other Methods

1. Direct Mapping

2. Associative (Fully Associative) Mapping

3. Set-Associative Mapping

Handshake Protocol of Asynchronous Data Transfer (14 Marks)

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