Instruction Cycle Phases:

1. Fetch (F): Address in PC is put on bus, instruction fetched from memory to IR, PC incremented to next instruction.

2. Decode (D): Control unit decodes opcode in IR, identifies instruction type, operand addressing modes, and generates control signals; operands fetched from registers.

3. Execute (E): ALU/Control performs operation - arithmetic/logic, effective address calculation, branch target evaluation.

4. Memory/Interrupt Check: If instruction needs memory access (LOAD/STORE) data transfer occurs; finally CPU checks for pending interrupts - if any, save context and branch to ISR.

Cycle repeats as: $Fetch \rightarrow Decode \rightarrow Execute \rightarrow Interrupt\ Check$.