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Module 3: Pipelining

20162m

Briefly explain the conflicts in instruction pipeline.

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Conflicts/Hazards in Instruction Pipeline: pipeline cannot overlap execution. Three types:

  1. Structural Hazard (Resource conflict): Two stages need same hardware resource in same cycle. e.g., single memory for instruction fetch and data access, single ALU. Solved by separate I-cache/D-cache, extra functional units, pipeline stalls.

  2. Data Hazard: Next instruction needs data not yet produced by previous instruction. Types: RAW (Read After Write - true dependency), WAR, WAW. Causes stalls/bubbles. Solved by forwarding/bypassing, register renaming, compiler scheduling.

  3. Control Hazard (Branch hazard): Due to branch/jump instructions. Pipeline doesn't know next PC until branch resolved, so wrong instructions fetched. Causes flushing. Solved by branch prediction, delayed branch, branch target buffer, prefetch.

All reduce speedup from ideal kk to <k<k and need hazard handling.

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