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COMPUTER ORGANIZATION & ARCHITECTURE(d) The instruction fetch phase ends with (i) placing the data from the address in MAR into MDR (ii) placing the address of the data into MAR (iii) completing the execution of the data and placing its storage address into MAR (iv) decoding the data in MDR and placing it in IR20222mCOMPUTER ORGANIZATION & ARCHITECTUREExplain fetch-decode-execution cycle.20147mCOMPUTER ORGANIZATION & ARCHITECTUREThe sequence of events that happen during a typical fetch operation is - (i) PC → MAR → Memory → MDR → IR - (ii) PC → Memory → MDR → IR - (iii) PC → Memory → IR - (iv) PC → MAR → Memory → IR20197mCOMPUTER ORGANIZATION & ARCHITECTUREThe unit responsible for fetching, decoding, and executing instructions is: (i) ALU (ii) Memory Unit (iii) Control Unit (iv) I/O Unit20252m
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