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COMPUTER ORGANIZATION & ARCHITECTURE(d) The instruction fetch phase ends with (i) placing the data from the address in MAR into MDR (ii) placing the address of the data into MAR (iii) completing the execution of the data and placing its storage address into MAR (iv) decoding the data in MDR and placing it in IR20222mCOMPUTER ORGANIZATION & ARCHITECTUREWhat is the first step in the instruction execution cycle? (i) Decode (ii) Fetch (iii) Execute (iv) Store20242mCOMPUTER ORGANIZATION & ARCHITECTUREExplain fetch-decode-execution cycle.20147mCOMPUTER ORGANIZATION & ARCHITECTUREThe unit responsible for fetching, decoding, and executing instructions is: (i) ALU (ii) Memory Unit (iii) Control Unit (iv) I/O Unit20252m
Previous(b) How is virtual memory managed using paging and TLB? Explain with suitable example.NextIn case of pipelining processor, loop buffer is * (i) very high speed memory maintained by the instruction fetch stage * (ii) very high speed memory maintained by the instruction decode stage * (iii) very high speed memory maintained by the instruction execute stage * (iv) None of the above