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Module 2: x86 Architecture, CPU Control, I/O, Memory System Design

20197m

The sequence of events that happen during a typical fetch operation is

  • (i) PC → MAR → Memory → MDR → IR
  • (ii) PC → Memory → MDR → IR
  • (iii) PC → Memory → IR
  • (iv) PC → MAR → Memory → IR
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Answer: (i) PC → MAR → Memory → MDR → IR

Typical Instruction Fetch Cycle (Fetch sequence) is:

  1. PC → MAR: Program Counter holds address of next instruction. Its content is transferred to Memory Address Register (MAR).
  2. MAR → Memory: MAR puts address on address bus, control unit issues READ.
  3. Memory → MDR: Instruction word read from memory is loaded into Memory Data Register (MDR) / MBR.
  4. MDR → IR: Instruction is then transferred to Instruction Register (IR) for decoding. Meanwhile PC is incremented (PC+1) to point to next instruction.

This is the standard von Neumann fetch path. Options (ii)-(iv) skip MAR or MDR and are incomplete.

Correct option: (i) PC → MAR → Memory → MDR → IR

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