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COMPUTER ORGANIZATION & ARCHITECTUREA computer with cache access time of 100\,ns, a main memory access time of 1000\,ns, and a hit ratio of 0.9 produces an average access time of (i) 250\,ns (ii) 200\,ns (iii) 190\,ns (iv) None of these20232mOPERATING SYSTEMConsider a demand-paging system with a paging disk that has an average access and transfer time of 20 milli-seconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time?20227mCOMPUTER ORGANIZATION & ARCHITECTUREThe minimum time delay between the initiations of two independent memory operations is called * (i) access time * (ii) cycle time * (iii) transfer rate * (iv) latency time20192mOperating SystemConsider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is 0.6, find the effective memory access time (in milliseconds).20227m
PreviousIn case of pipelining processor, loop buffer is * (i) very high speed memory maintained by the instruction fetch stage * (ii) very high speed memory maintained by the instruction decode stage * (iii) very high speed memory maintained by the instruction execute stage * (iv) None of the aboveNextThe minimum time delay between the initiations of two independent memory operations is called * (i) access time * (ii) cycle time * (iii) transfer rate * (iv) latency time