2019 question paper
COMPUTER ORGANIZATION & ARCHITECTURE
25 questions
Q1a. How many 128×8 bit RAMs are required to design 32 k x 32 bit RAM? - (i) 512 - (ii) 128 - (iii) 1024 - (iv) 3220192m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →How many 128×8 bit RAMs are required to design 32 k x 32 bit RAM?
- (i) 512
- (ii) 128
- (iii) 1024
- (iv) 32
Q1b. The intradata transfer techniques are implemented using - (i) serial I/O - (ii) parallel 1/0 - (iii) Both (i) and (ii) - (iv) Neither (i) nor (ii)20192m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →The intradata transfer techniques are implemented using
- (i) serial I/O
- (ii) parallel 1/0
- (iii) Both (i) and (ii)
- (iv) Neither (i) nor (ii)
Q1b. (b) How is virtual memory managed using paging and TLB? Explain with suitable example.20197m
Module 4: Memory Organization
View this question on its own page →(b) How is virtual memory managed using paging and TLB? Explain with suitable example.
Q1c. The sequence of events that happen during a typical fetch operation is - (i) PC → MAR → Memory → MDR → IR - (ii) PC → Memory → MDR → IR - (iii) PC → Memory → IR - (iv) PC → MAR → Memory → IR20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →The sequence of events that happen during a typical fetch operation is
- (i) PC → MAR → Memory → MDR → IR
- (ii) PC → Memory → MDR → IR
- (iii) PC → Memory → IR
- (iv) PC → MAR → Memory → IR
Q1c. In case of pipelining processor, loop buffer is * (i) very high speed memory maintained by the instruction fetch stage * (ii) very high speed memory maintained by the instruction decode stage * (iii) very high speed memory maintained by the instruction execute stage * (iv) None of the above20192m
Module 3: Pipelining
View this question on its own page →In case of pipelining processor, loop buffer is
- (i) very high speed memory maintained by the instruction fetch stage
- (ii) very high speed memory maintained by the instruction decode stage
- (iii) very high speed memory maintained by the instruction execute stage
- (iv) None of the above
Q1e. The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is * (i) 55 ns * (ii) 45 ns * (iii) 90 ns * (iv) 19 ns20192m
Module 4: Memory Organization
View this question on its own page →The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is
- (i) 55 ns
- (ii) 45 ns
- (iii) 90 ns
- (iv) 19 ns
Q1f. The minimum time delay between the initiations of two independent memory operations is called * (i) access time * (ii) cycle time * (iii) transfer rate * (iv) latency time20192m
Module 4: Memory Organization
View this question on its own page →The minimum time delay between the initiations of two independent memory operations is called
- (i) access time
- (ii) cycle time
- (iii) transfer rate
- (iv) latency time
Q1g. In case of vectored interrupt, interrupt vector means * (i) the branch information from the source which interrupts the system * (ii) an address that points to a location in memory where the beginning address of the I/O service routine is stored * (iii) Both (i) and (ii) * (iv) None of the above20192m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →In case of vectored interrupt, interrupt vector means
- (i) the branch information from the source which interrupts the system
- (ii) an address that points to a location in memory where the beginning address of the I/O service routine is stored
- (iii) Both (i) and (ii)
- (iv) None of the above
Q1i. A microprogrammed control unit * (i) is faster than a hardwired control unit * (ii) facilitates easy implementation of new instructions * (iii) is useful when every small program is to be run * (iv) usually refers to the control unit of the microprocessor20192m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →A microprogrammed control unit
- (i) is faster than a hardwired control unit
- (ii) facilitates easy implementation of new instructions
- (iii) is useful when every small program is to be run
- (iv) usually refers to the control unit of the microprocessor
Q1j. Which of the following holds data and processing instructions temporarily until the CPU needs it? * (i) ROM * (ii) Control unit * (iii) Main memory * (iv) Coprocessor chip20192m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Which of the following holds data and processing instructions temporarily until the CPU needs it?
- (i) ROM
- (ii) Control unit
- (iii) Main memory
- (iv) Coprocessor chip
Q2a. How do instruction set, compiler technology, CPU implementation and control, and cache and memory hierarchy affect the CPU performance? Justify the effects in terms of program length, clock rate and effective CPI.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →How do instruction set, compiler technology, CPU implementation and control, and cache and memory hierarchy affect the CPU performance? Justify the effects in terms of program length, clock rate and effective CPI.
Q3a. Explain register reference and memory reference instructions in detail with suitable examples.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain register reference and memory reference instructions in detail with suitable examples.
Q3b. Draw the block diagram of control unit of basic computer. Explain in detail with control timing diagrams.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Draw the block diagram of control unit of basic computer. Explain in detail with control timing diagrams.
Q4a. Explain one-, two- and three-address instruction with suitable examples.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain one-, two- and three-address instruction with suitable examples.
Q4b. Give an integrated diagram showing the TLB and cache operations for a logical/virtual address generated by a processor.20197m
Module 4: Memory Organization
View this question on its own page →Give an integrated diagram showing the TLB and cache operations for a logical/virtual address generated by a processor.
Q5a. Explain the daisy chaining mechanism for bus arbitration. Analyze the three bus arbitration methods – daisy chaining, polling, and independent requesting – with respect to communication reliability in the event of hardware failures.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain the daisy chaining mechanism for bus arbitration. Analyze the three bus arbitration methods – daisy chaining, polling, and independent requesting – with respect to communication reliability in the event of hardware failures.
Q5b. Give the block diagram of the microprogram sequencer for a control memory and explain it properly.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Give the block diagram of the microprogram sequencer for a control memory and explain it properly.
Q6a. What do you understand by hardwired control? Give various methods to design a hardwired control unit. Describe any one with a suitable example.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What do you understand by hardwired control? Give various methods to design a hardwired control unit. Describe any one with a suitable example.
Q6b. Describe autoincrement and decrement addressing modes with proper examples.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Describe autoincrement and decrement addressing modes with proper examples.
Q7a. What is Direct Memory Access (DMA)? Explain. Give the block diagram of circuitry required for direct memory access.20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What is Direct Memory Access (DMA)? Explain. Give the block diagram of circuitry required for direct memory access.
Q7b. A digital computer has a common bus system of 16 registers of 32 bits each. The bus is constructed with multiplexers. - (i) How many selection inputs are there in each multiplexer? - (ii) What size of multiplexers is needed?20197m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →A digital computer has a common bus system of 16 registers of 32 bits each. The bus is constructed with multiplexers.
- (i) How many selection inputs are there in each multiplexer?
- (ii) What size of multiplexers is needed?
Q8a. When do you say the floating point number is normalized? Explain how floating point representation of number is done. Represent the number (+46.25) as floating point binary number with 32 bits.20197m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →When do you say the floating point number is normalized? Explain how floating point representation of number is done. Represent the number (+46.25) as floating point binary number with 32 bits.
Q8b. What are hazards in pipeline architecture? Explain its types with suitable examples.20197m
Module 3: Pipelining
View this question on its own page →What are hazards in pipeline architecture? Explain its types with suitable examples.
Q9a. What is an array processor? Explain SIMD array processor with a suitable example.20197m
Module 3: Pipelining
View this question on its own page →What is an array processor? Explain SIMD array processor with a suitable example.
Q9b. A DMA controller transfers 16-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at the rate of 2400 characters per second. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of DMA transfer?20197m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →A DMA controller transfers 16-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at the rate of 2400 characters per second. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of DMA transfer?