Virtual Memory, Paging and TLB

Virtual Memory: Technique that allows execution of program larger than physical main memory by using disk (swap) as extension. CPU generates virtual/logical address, translated by MMU to physical address. Gives programmer illusion of large contiguous memory and provides isolation/protection.

Paging: Virtual and physical memory divided into fixed equal blocks - pages (virtual) and frames (physical), e.g. 4KB. Virtual address = [Virtual Page Number (VPN) | Offset]. Page Table stores mapping VPN -> Frame No. + valid/dirty/protection bits. On page fault (valid=0), OS brings page from disk, updates table.

Example: 32-bit virtual addr, 4KB pages (offset 12 bits). VA = 0x00403ABC -> VPN = 0x00403, Offset=0xABC. Page Table[0x00403]= Frame 0x00A -> PA=0x00AABC.

TLB - Translation Lookaside Buffer: Small, fully-associative high-speed cache of recently used Page Table Entries inside MMU.

• TLB Hit: VPN found in TLB -> frame number returned in ~1 cycle, no memory access.
• TLB Miss: Search page table in memory (or walk), load entry into TLB, may cause page fault.

Effective Access Time: $EAT = h \cdot (c+ m) + (1-h)(c+2m)$ where $h$= hit ratio, $c$= TLB time, $m$= memory time. With $h \approx 98\%$, EAT $\approx$ memory speed. TLB greatly reduces translation overhead. Replacement via LRU/random, flush on context switch.