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Module 5: Memory Management

20237m

Explain paging with translation look-aside buffer (TLB) scheme with suitable diagrams.

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Paging + TLB

Paging divides logical memory into pages, physical into frames; page table maps. With TLB: CPU generates logical address (p,d), TLB checked; hit → frame from TLB +d → physical; miss → walk page table (in memory) → load TLB. Diagram: Logical → TLB? → Frame → Physical. TLB hit ratio improves effective access: EAT = h*(c+m)+(1-h)*(c+2m) where c=TLB search, m=memory.

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