TLB and Cache Operations for Virtual Address

Virtual (Logical) address from CPU is translated to Physical address via TLB + Page Table, then Physical address accesses Cache + Main Memory.

Address Split Example (32-bit VA, 4KB pages, 32KB 4-way cache 64B blocks)

• VA: Virtual Page Number (VPN) | Page Offset (12 bits) (20+12 for 4KB)
• PA: Physical Page Number (PPN) | Page Offset
• PA for cache: Tag | Set | Block Offset (e.g., PPN part provides Tag+Set)

Integrated Flow

CPU generates VIRTUAL ADDRESS (VA)
            |
            v
      +------------+      TLB Hit (80-99%)       +-----------------+
      |    TLB     | --------------------------->|   CACHE         |
      |(Translation|  VPN -> PPN translation    | (Physically     |
      | Lookaside  |                             |  tagged/indexed)|
      | Buffer)    |  TLB Miss -> Page Table     |                 |
      | CAM 64-1024|  walk (hardware / OS)       | Tag | Set | Off |
      +------------+  -> refill TLB              +--------+--------+
            |                                      |Hit | Miss
            | Miss                                 v      v
      +------------+                          +-------+ +--------+
      | Page Table |                          | Data to CPU | Main Memory |
      | in Memory  |                          +-------+  (fetch block -> cache)
      |(2-level)   |
      +------------+
            |
            v
      Physical Address (PA) = PPN + offset  ---> to Cache & Memory protection check

Step-by-Step Operations

1. CPU issues VA: VPN + Offset. Also permission bits checked.

2. TLB Lookup (parallel with cache - virtually indexed):

   • TLB Hit: CAM compares VPN with all entries (valid+ASID). Returns PPN in ~1 cycle. Form PA = PPN || offset.
   • TLB Miss: Hardware page table walker reads page table in memory (2-4 accesses for multi-level), brings PTE to TLB. If page not in memory -> Page Fault -> OS loads from disk.

3. Cache Access (using PA - physically indexed physically tagged PIPT, most common):

   • Decode PA: Set = (PA >> blockOffset) % sets, compare Tag array for that set (4-way).
   • Cache Hit: Data returned to CPU (~4-10 cycles L1). No memory access.
   • Cache Miss: Request goes to L2/L3 / Main Memory; block (64B) fetched to cache line (with Tag), then to CPU. TLB and cache may be accessed in parallel or sequentially depending on design:
     • PIPT: TLB first, then cache (safe, needs translation).
     • VIPT: Index with VA bits (no alias), Tag with PA -> overlaps TLB.
     • VIVT: Both virtual - needs flush on context switch.

4. Overlap / Virtually Indexed Physically Tagged (VIPT) optimization: L1 cache can start set decode using page offset bits (12 bits = not translated) while TLB translates VPN. On translation complete, tag compare uses PPN.

Protection & Extras

• TLB PTE contains Valid, Dirty, Referenced, R/W/X, U/S, Cacheability bits - checked on translation.
• On context switch, TLB flush or ASID-tagged entries avoid flush.
• Multi-level Inclusive TLB + L1/L2 Cache hierarchy: TLB miss cost 20-100 cycles; Page fault ms.

Summary: VA -> TLB (VPN->PPN) -> PA -> Cache(Tag/Set match) -> Hit? -> CPU : Memory. TLB is cache for page table, Cache is cache for memory blocks.