Virtual Memory Concept

Virtual memory is a memory management technique that gives program illusion of large contiguous main memory (e.g. $4$ GB) while physically only part resides in RAM; remainder kept on secondary storage (disk). Address generated by CPU (virtual/logical) is translated to physical via MMU.

CPU generates              MMU + Page Table + TLB                Main Memory / Disk
Virtual Address  ----->   Translation  -----> Physical Address ---> RAM (if present)
  32-bit                    VPN -> PFN       32-bit              else Page Fault -> Disk

• Virtual address space $>>$ Physical address space (e.g. $2^{32}$ virtual vs $2^{28}$ physical).
• Transparent to programmer, allows multiprogramming, protection, demand paging.
• Uses locality – only active pages kept in RAM.

Diagram: Paged Virtual Memory Mapping

Virtual Address (32b)
+----------------------+------------------+
| Virtual Page Number  | Page Offset      |
|  VPN (20b)           |  OFFSET (12b)    |  -> 4KB pages
+-----------+----------+-----+------------+
            |                  |
            v                  |
     +--------------+          |
     | Page Table   | TLB      |
     | (in RAM)     | cache    |
     | VPN -> PFN   |          |
     +------+-------+          |
            |                  |
            v                  v
Physical Address (32b)
+----------------------+------------------+
| Physical Frame Number| Offset           |
|  PFN (20b)           | (12b same)       |
+----------------------+------------------+

RAM: [Frame 0][Frame 1]...[Frame N]   Disk: swap space with all pages

Virtual to Physical Mapping Steps (Paging)

Assume page size $4$ KB $=2^{12}$ B $\Rightarrow$ offset $12$ bits, VPN $20$ bits for $32$-bit virtual.

1. CPU generates virtual address $VA = (VPN, offset)$.
2. MMU looks up TLB (Translation Lookaside Buffer) – cache of page table.
   • TLB hit: get PFN immediately.
   • TLB miss: access page table in RAM (pointed by Page Table Base Register - PTBR). May be multi-level (e.g. 2-level for 32-bit).
3. Page Table Entry (PTE) contains: PFN, valid bit, dirty, protection (R/W/X), referenced.
   • If valid=1: $PA = PFN \times PAGE\_SIZE + offset$ (concatenation).
   • If valid=0: Page Fault → trap to OS. OS loads required page from disk to free frame (using replacement e.g. LRU), updates PTE, restarts instruction.
4. Physical address sent to cache/memory.

Example: $VA=0x12345678$, page $4$ KB $\Rightarrow$ VPN=$0x12345$, offset=$0x678$; page table maps VPN $0x12345 \rightarrow PFN 0x00ABC$ $\Rightarrow$ $PA=0x00ABC678$.

Segmentation + Paging: Sometimes VA = segment + offset; segment table → page table. But pure paging described above is most common (x86, ARM).

Advantages: Large logical space, protection/isolation, sharing, efficient multiprogramming, demand loading.

Overhead: Translation time (mitigated by TLB $>95\%$ hit), page fault handling, fragmentation (internal).