2017 question paper
COMPUTER ORGANIZATION & ARCHITECTURE
16 questions
Q1a. Write the range of decimal integer that can be represented by n-bit 2’s complement representation.20172m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Write the range of decimal integer that can be represented by n-bit 2’s complement representation.
Q1b. Justify the statement “Stack computer consists of an operation code only with no address field”.20172m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Justify the statement “Stack computer consists of an operation code only with no address field”.
Q1c. What do you mean by Arithmetic shift left operation?20172m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What do you mean by Arithmetic shift left operation?
Q1d. What do you mean by locality of reference?20172m
Module 4: Memory Organization
View this question on its own page →What do you mean by locality of reference?
Q1e. What are the properties of an ideal instruction set computer?20172m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What are the properties of an ideal instruction set computer?
Q1f. Define the term hardware polling.20172m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Define the term hardware polling.
Q1g. What do you mean by data hazards in pipelining?20172m
Module 3: Pipelining
View this question on its own page →What do you mean by data hazards in pipelining?
Q1h. Explain indirect address mode, and how the effective address is calculated in this case.20172m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Explain indirect address mode, and how the effective address is calculated in this case.
Q2. Why is read and write control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs?201714m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Why is read and write control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs?
Q3. Explain the concept of virtual memory with the help of a diagram. Explain how virtual address is mapped to actual physical address.201714m
Module 4: Memory Organization
View this question on its own page →Explain the concept of virtual memory with the help of a diagram. Explain how virtual address is mapped to actual physical address.
Q4. What is meant by Addressing Mode? Explain at least five different addressing modes with an example.201714m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →What is meant by Addressing Mode? Explain at least five different addressing modes with an example.
Q5. What are the different conflicts that will arise in pipeline (elaborate)? How do you remove the conflicts?201714m
Module 3: Pipelining
View this question on its own page →What are the different conflicts that will arise in pipeline (elaborate)? How do you remove the conflicts?
Q6. Explain Von Neumann Architecture. What are its drawbacks?201714m
Module 1: Functional Block of computer and Data representaion
View this question on its own page →Explain Von Neumann Architecture. What are its drawbacks?
Q7. What is a page fault? What does a page fault signify? Explain the different page replacement algorithms which determine the page to be removed in case of full memory.201714m
Module 4: Memory Organization
View this question on its own page →What is a page fault? What does a page fault signify? Explain the different page replacement algorithms which determine the page to be removed in case of full memory.
Q8. Why does I/O interrupt make more efficient use of the CPU? Explain the sequence of operations that take place in an interrupt-driven I/O transfer.201714m
Module 2: x86 Architecture, CPU Control, I/O, Memory System Design
View this question on its own page →Why does I/O interrupt make more efficient use of the CPU? Explain the sequence of operations that take place in an interrupt-driven I/O transfer.
Q9. How many ROM chips are required to produce a memory capacity of 4096 bytes? How many address lines are required to access the 4096 bytes? How many of these addresses will be common to all these chips?201714m
Module 4: Memory Organization
View this question on its own page →How many ROM chips are required to produce a memory capacity of 4096 bytes? How many address lines are required to access the 4096 bytes? How many of these addresses will be common to all these chips?