Von Neumann Architecture

Proposed by John von Neumann (1945, EDVAC report). Also called Stored-Program Concept and Princeton Architecture. Dominant architecture for general-purpose computers.

1. Principle

Program (sequence of instructions) and data are stored together in the same read-write memory and treated alike. CPU fetches instructions sequentially from memory, decodes and executes them, modifying data in same memory.

2. Block Diagram

                  +----------------------------------+
                  |        Central Processing Unit     |
                  |   +------------------+  +------+  |
                  |   | Control Unit (CU)|  | ALU  |  |
   Input Device -->|   |  - PC            |<-+      |  |
   (Keyboard,     |   |  - IR            |  |      |  |
    Disk)         |   |  - Decodes inst. |->+      |  |
                  |   +------------------+  +------+  |
                  |            ^   |    ^             |
                  |            |   v    |             |
                  +------------+---+----+-------------+
                               |   |    |
                          +----+---v----+----+
                          |      Memory       |
                          |  (Single Address  |
                          |   Space for       |
                          | Program + Data)   |
                          +---------+---------+
                                    ^   |
                  +-----------------+   +--v---------------+
                  | Output Device   |<-----| I/O Interface |
                  | (Display, etc)  |      +---------------+
                  +---------------+

Simplified bus view:

  +----------------+     Address Bus
  |      CPU       |<---------------->+----------------+
  |  CU + ALU +    |     Data Bus     |    Memory      |
  |  Registers     |<---------------->| (Instructions  |
  +----------------+   Control Bus    |  + Data)       |
         ^                            +----------------+
         |                            |
         +------> I/O Module ---------> Devices

Core components:

1. Memory (M): Single linear address space, stores both instructions and data. Each location has unique address.
2. Control Unit (CU): Fetches instruction at M[PC], increments PC, decodes opcode, generates control signals, coordinates fetch-decode-execute cycle.
3. ALU: Performs arithmetic/logic on data from registers/memory.
4. Registers: PC, IR, MAR, MBR, Accumulator/GPRs inside CPU.
5. I/O: Input/Output mechanism via same bus.

Operation Cycle (Fetch-Decode-Execute):

1. Fetch: MAR <- PC; MBR <- M[MAR]; IR <- MBR; PC <- PC+1
2. Decode: CU decodes IR
3. Execute: ALU or memory operation as per opcode; repeat

3. Characteristics

• Single memory bus for instructions and data (sequential access).
• Instruction execution is sequential unless branch modifies PC.
• Hardware simple - one memory, one bus.

4. Drawbacks / Limitations

1. Von Neumann Bottleneck: Single bus between CPU and memory can only transfer one word at a time - cannot fetch instruction and access data simultaneously. CPU stalls waiting for memory (memory wall). Limits throughput even if CPU is fast.

2. Sequential execution: No inherent parallelism; instruction-level parallelism must be extracted via pipelining/cache which complicates control.

3. Memory is limiting factor: CPU speed >> memory speed, bottleneck dominates performance.

4. Shared bus contention: I/O and CPU compete for same memory bus.

5. Not suitable for real-time DSP: Harvard architecture (separate instruction and data memories/buses) used in DSP/microcontrollers for simultaneous fetch to overcome this - Von Neumann lacks that.

6. Virus/security issue: Since code and data share same memory, erroneous data can be executed as code (buffer overflow attacks).

Improvement: Modern computers keep Von Neumann logically but implement Harvard-like cache (split L1 I-cache/D-cache), pipeline, out-of-order execution, and hierarchy to hide bottleneck while retaining stored-program simplicity.