ROM Chip Calculation for 4096 Bytes (14 Marks)

Given: Required memory capacity = 4096 bytes = $4096 \times 8 = 32768$ bits.
Let ROM chip capacity be $C$ bytes/chip. Standard chips often $512 \times 4$, $1024 \times 4$, $1024 \times 8$ etc. General formulae below; numerical example for most common exam assumption follows.

General Formulae:

1. Number of chips $N = \frac{\text{Required capacity}}{\text{Chip capacity}}$
2. Number of address lines to access 4096 bytes: $2^{k}=4096 \Rightarrow k=\log_2 4096 =12$ lines ($A_{11}$-$A_{0}$)
3. Common addresses: Address lines are split into chip-select (higher) + intra-chip (lower). Lower $m$ lines where $2^{m}= \text{chip size in bytes}$ go to all chips in parallel (common), upper $(k-m)$ lines go to decoder to generate chip selects.

Worked Example – Assume typical exam chip $512 \times 4$ bit (512 nibbles = 256 bytes? often quoted as 1024×4):

Most textbooks assume $1024 \times 4$ bit ROM (128 bytes? actually $1024 \times 4 =4096$ bits =512 bytes) or $512 \times 8$ (512 bytes).

Case A: If chip = $1024 \times 8$ (1024 bytes = 1 KB) – commonest for 4096:

• $N = 4096/1024 = 4$ chips
• Address lines =12
• Per chip needs $\log_2 1024=10$ lines ($A_9$-$A_0$) common to all 4 chips (connected in parallel)
• Remaining $12-10=2$ lines ($A_{11}A_{10}$) decoded via 2:4 decoder for chip select. So 10 common address lines, 2 chip-select lines.

Case B: If chip = $512 \times 4$ bit = 256 bytes? Many colleges treat chip as $512$ bytes ($512 \times 8$):

• $N =4096/512=8$ chips
• Per chip needs 9 lines ($\log_2 512=9$) common to all 8 chips
• Remaining 3 lines decoded via 3:8 decoder. So 9 common lines.

Case C: If chip = $512 \times 4$ bit = 2048 bits =256 bytes and need byte organized memory: Need 2 chips per byte location (pair to make 8 bits), so $N=(4096 \times 8)/(512 \times 4)=16$ chips. Per chip 9 lines common? Actually 9 lines for 512 locations, 4 lines common? Detailed: $16$ chips arranged as 8 rows ×2 columns, $A_8$-$A_0$ (9 lines) common to all, $A_{11}$-$A_9$ (3 lines) to 3:8 decoder.

Answer in generic terms:

• Chips required = $4096 / C$ (e.g., $4$ for 1K×8, $8$ for 512×8, $16$ for 512×4)
• Address lines =12
• Common lines = $\log_2(C)$ to all chips (e.g., 10 lines for 1K chips, 9 for 512-byte chips), remaining lines are chip-select decoded.

Without loss, exam expects: 8 chips of 512 bytes, 12 address lines, 9 common (if 512-byte assumed) or 4 chips, 10 common (if 1K assumed). State assumption explicitly.