Data Hazards (RAW) Definition (2 Marks)

In a pipelined processor, a data hazard occurs when an instruction depends on result of a previous instruction still in pipeline and data is not yet available.

RAW (Read After Write) - True dependence: Most common type.

I1: ADD R1, R2, R3   // R1 ← R2+R3
I2: SUB R4, R1, R5   // needs R1

I2 reads R1 before I1 writes it. If I2 enters ID/EX while I1 still in EX/MEM, it reads stale value — incorrect execution.

Handling: Data forwarding/bypassing from MEM/WB to ALU input, pipeline stalling (bubble/NOP), compiler reordering.

Other types WAW and WAR cause hazards only in out-of-order pipelines.