Hazards in Pipeline Architecture (7 Marks)

Pipelining overlaps fetch-decode-execute stages to increase throughput (ideal CPI=1). Hazards prevent next instruction from executing in designated cycle, causing stalls/bubbles.

1. Structural Hazards – Resource Conflict
Two instructions need same hardware at same time.
Example: Single memory for instruction + data. Stage IF and MEM both need memory in same cycle. Solution: separate I-Cache/D-Cache (Harvard) or stall.
Other examples: Single ALU used for EX and address calculation; insufficient registers ports.

2. Data Hazards – Data Dependency
Occurs when instruction depends on result of previous instruction not yet completed. Three types:

a) RAW (Read After Write) – True Dependency: $I2$ reads register $I1$ writes.

ADD R1,R2,R3   ; R1 written
SUB R4,R1,R5   ; R1 read – needs forwarding/stall

Most common. Solved by forwarding/bypassing, operand forwarding, compiler reordering, stalling.

b) WAR (Write After Read) – Anti-Dependency:

ADD R4,R1,R5
SUB R1,R2,R3   ; writes R1 before first reads it

Not in classic 5-stage in-order pipeline but appears in out-of-order execution. Solved by register renaming.

c) WAW (Write After Write) – Output Dependency:

ADD R1,R2,R3
SUB R1,R4,R5   ; both write R1

Also for out-of-order. Solved by renaming.

3. Control Hazards (Branch Hazards)
Caused by branches/jumps – next PC unknown until branch resolved.

BEQ R1,R2, LABEL ; whether to take branch known in EX/MEM
ADD R3,R4,R5     ; next instruction fetched incorrectly if branch taken

Penalty = flush pipeline. Solutions:

• Stall until decision known
• Branch prediction (static: predict not taken; dynamic: 1-bit/2-bit predictor, BTB)
• Delayed branch (fill delay slot with useful/no-op instruction)
• Speculative execution

All hazards reduce speedup: $Speedup = \frac{n}{\text{ideal cycles + stalls}}$.